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參數(shù)資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 77/88頁 |
| 文件大?。?/td> | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
77
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
Notes
1.
The measurement of the maximum value is done with all output pins disconnected; V
IL
= V
SS
; V
IH
= V
DD
; RST = V
DD
;
XTAL1 driven with square wave; XTAL2 not connected; all derivative blocks disabled. To see the typical value of
each instruction please consult Table 78 “Instruction set”.
The minimum operating voltage is the level where VDD is higher than the power-on reset level.
For this measurement an instruction was selected which current consumption is around the typical value;
the instruction is: LJMP to ADDR + 03H.
The typical operating supply current is evaluated as a mean value over all possible instructions (100% CPU load)
and with a crystal connected.
Verified on sampling basis.
The Idle mode supply current is measured with all output pins and RST disconnected; V
IL
= V
SS
; V
IH
= V
DD
;
XTAL1 driven with square wave; XTAL2 not connected; all derivative blocks disabled.
The Power-down mode supply current is measured with all output pins and RST disconnected; V
IL
= V
SS
; V
IH
= V
DD
;
XTAL1 and XTAL2 not connected.
The typical currents are only for the specific block. To calculate the typical power consumption of the microcontroller,
the current consumption of the CPU weighted with the processing must be added. Example: the typical average
current consumption of the microcontroller in operating mode with 10% CPU processing load, Watchdog timer and
MSK active can be calculated as: 10%
×
I
CPU
+ I
DD(id)
+ I
WD
+ I
MSK
.
For some peripheral blocks it could be required to reduce the internal clock frequency with the PSC2 and an
additional divider inside the peripherals. Symbol ‘f
XTAL1
’ is meant for external device clocking and ‘f
osc
’ is meant as
on-chip oscillator frequency.
10. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I
2
C-bus specification. Therefore, an input voltage
below 0.3V
DD
will be recognized as a logic 0 and an input voltage above 0.7V
DD
will be recognized as a logic 1.
11. Not valid for pins SDA, SCL, RST and MIN.
12. Due to the maximum allowed current, the number of output pins switching at the same time should be limited to one.
2.
3.
4.
5.
6.
7.
8.
9.
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參數(shù)描述 |
|---|---|
| P83CL882T/001 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 Ultra Low Power ULP telephony controller |
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