參數(shù)資料
型號(hào)： P83CL882
廠商： NXP Semiconductors N.V.
英文描述： 80C51 Ultra Low Power ULP telephony controller
中文描述： 80C51的超低功耗無(wú)鉛汽油電話控制器
文件頁(yè)數(shù)： 71/88頁(yè)
文件大?。?/td> 328K
代理商： P83CL882
2001 Jun 19
71
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
8
APPLICATION INFORMATION
8.1
Introduction
This chapter presents some information about how to use
the P83CL882 in an application. It is not intended to
replace the application notes but serves as a quick help
when starting to work with the Philips Ultra Low Power
handshake microcontrollers. There are some important
improvements between the silicon in plastic packages and
the Metalink EH emulator system which are described
here. Furthermore, some hints on software development
and power consumption are given to help the user take
advantage of the full benefits of the handshake CPU.
8.2
Differences between P83CL882 and the
Metalink EH emulation system
The SYSCON SFR does not exist on the emulator
system
On the emulator the oscillator can only be used in
normal mode which is the default start-up mode of the
P83CL882. The hysteresis input comparator does not
exist
The clock source of the Timer 0 and 1 is always f
psc
on
the emulator system. The timers can be used as
counters, counting from external pin T1 or T0 but this is
not possible in Power-down mode.
The interrupts T0 and T1 can cause on the emulator
only a wake-up from idle and not from power-down
Prescaler bits PRESC[7:5] are not available on the
emulator; therefore the synchronous mode and clock
out functionality is not present
MSK polarity cannot be inverted on the emulator
INT1 interrupt is on the emulator version present on
P3.3 where it is mapped on P3.1 on the P83CL882
The clock output on P1.4 does not exist on the emulator.
8.3
The asynchronous handshake CPU
As the CPU of the P83CL882 is built in asynchronous
technology (hand-shake mechanism) some properties are
singular to it in comparison to standard synchronous
80C51 controllers:
The CPU itself does not need a clock for code execution
The performance (MIPs) is not dependent on oscillator
frequency but strongly related to V
DD
, temperature,
silicon parameters and type of software. It always runs
at the maximum speed determined by the external
influences above. Therefore, it operates also with the
maximum power consumption in the minimum time.
Generally the lower the temperature and the higher the
V
DD
the faster the CPU runs. Details on instruction
speed and energy consumption per instruction can be
found in Chapter 7.
Because of the above mentioned properties some hints
are given for using this controller in any kind of application
in an efficient way.
Due to the high CPU performance, independent of clock
frequency, certain functions (e.g. serial or customized
interfaces) can be built in software in a very efficient and
flexible way.
In classic 80C51 software the user (software engineer)
was able to rely on cycle-timing for wait-loops,
synchronisation in the system or similar usage (e.g.
NOP instruction for waiting one machine cycle). When
using the asynchronous CPU wait-loops should be
implemented by starting a timer and putting the CPU in
Idle mode in order to wait for an interrupt. Significant
power reduction and a much more robust software will
be obtained. If in an application the instruction counter is
needed Timer 0 or 1 can be used with the instruction
request signal connected to the clock source input.
One should avoid using ‘wait-until’-loops (SFR polling).
This would lead to maximum CPU-load resulting in very
high current consumption. The CPU should always be
used as an event driven machine waiting for interrupts.
After an activity the device must be entered in Idle or
Power-down mode as fast as possible, the current is
then reduced down to leakage. The device provides
flexible means (interrupts, timer, counters) for
a recovery from these power reduction modes.
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