參數(shù)資料
型號： P83CL882
廠商： NXP Semiconductors N.V.
英文描述： 80C51 Ultra Low Power ULP telephony controller
中文描述： 80C51的超低功耗無鉛汽油電話控制器
文件頁數(shù)： 43/88頁
文件大?。?/td> 328K
代理商： P83CL882
2001 Jun 19
43
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.7
Watchdog Timer
The Watchdog Timer consists of an 8-bit down counter
and a Watchdog prescaler. The binary number defined by
bitsWD3 to WD0(WDCONSFR),theWatchdogprescaler
and the timer prescaler (f
psc
) defines the expiration time of
the Watchdog Timer. Once enabled this counter runs
continuously. Once expired the timer produces firstly an
interrupt and finally a reset. The software must reload the
Watchdog Timer at regular intervals to avoid expiration.
A positive edge on bit LD (WDCON SFR) (re)loads the
counter with the value of WD3 to WD0, sets the LOW bits
to logic 1 and activates this counter if it is not yet running.
However, to prepare the (re)loading a positive edge must
be applied to the COND bit in WDCON.
In this way at least two locations in software are needed
before the counter can be reloaded.
After reset the counter is not running. Only after the first
load (LD) it is clocked continuously by a clock pulse.
If the next LD signal is not given within the defined
expiration interval an overflow occurs and the processor
will be reset (signal WDR). One clock cycle (seen from the
Watchdog prescaler output) before the reset is applied a
WDI interrupt is issued. This gives the opportunity to avoid
the reset if required. The maximum Watchdog Timer
expiration time is thus 254/f
psc
to the WD interrupt and
255/f
psc
to the reset.
6.7.1
W
ATCHDOG
T
IMER
C
ONTROL
R
EGISTER
(WDCON)
The WDCON SFR is used to control the operation of the on-chip Watchdog Timer. If the Watchdog Timer is not loaded
after reset, the clock to the Watchdog Timer is switched off for power saving.
Table 53
Watchdog Timer Control Register (SFR address A5H; reset value = 0000 0000)
Table 54
Description of WDCON bits
7
6
5
4
3
2
1
0
COND
WD3
WD2
WD1
WD0
MSKPOL
LD
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
COND
WD3
WD2
WD1
WD0
MSKPOL
load condition; control signal from processor
WD0 to WD3 is the preset value for the high nibble of the Watchdog Timer
this bit controls the polarity of the input signal to the MSK modem;
MSKPOL = 0: input directly connected to the MSK modem
MSKPOL = 1: input inverted and connected to the MSK modem
reserved, must be kept to logic 0
load Watchdog Timer with WD0 to WD3; control signal from CPU
1
0
LD
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