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參數(shù)資料
| 型號(hào)： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 49/88頁 |
| 文件大小： | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
49
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.8.3
A
DDRESS
R
EGISTER
(S1ADR)
The CPU can read from and write to this 8-bit SFR. S1ADR is not affected by the SIO1 hardware. The contents of this
register are irrelevant when SIO1 is in a Master mode.
In the Slave modes, the seven most significant bits must be loaded with the microcontrollers own slave address, and, if
the least significant bit is set, the general call address (00H) is recognized; otherwise it is ignored. Reset initializes
S1ADR to 00H.
Table 62
Address Register (SFR address DBH)
Table 63
Description of S1ADR bits
6.8.4
S
ERIAL
S
TATUS
R
EGISTER
(S1STA)
S1STA is an 8-bit read-only Special Function Register. The three least significant bits are always zero. The five most
significant bits contain the status code. There are 26 possible status codes. When S1STA contains F8H, no relevant
state information is available and no serial interrupt is requested. Reset initializes S1STA to F8H. All other S1STA values
correspond to defined SIO1 states. When each of these states is entered, a serial interrupt is requested (SI = 1).
The status codes for all possible modes of the I
2
C-bus interface are given in Table 66.
The contents of this register may be used as a vector to a service routine. This optimizes the response time of the
software and consequently that of the I
2
C-bus. S1STA is a read-only register.
Table 64
Serial Status Register (SFR address D9H)
Table 65
Description of S1STA bits
7
6
5
4
3
2
1
0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
GC
BIT
SYMBOL
DESCRIPTION
7 to 1
SLA[6:0]
These bits correspond to the 7-bit slave address which will be recognized on the
incoming data stream from the I
2
C-bus; when the slave address is detected and the
interface is enabled, a serial interrupt will be generated to the CPU.
This bit is used to determine whether the general CALL address is recognized. When a
logic 0, the general CALL address is not recognized; when a logic 1, the general CALL
address is recognized.
0
GC
7
6
5
4
3
2
1
0
SC4
SC3
SC2
SC1
SC0
0
0
0
BIT
SYMBOL
DESCRIPTION
3 to 7
0 to 2
SC[4:0]
5-bit status code
these three bits are held LOW
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