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參數(shù)資料
| 型號(hào)： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 29/88頁 |
| 文件大?。?/td> | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
29
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.4
Port control logic
Four 8-bit I/O ports are implemented in the device. Some
of these general purpose I/Os are multiplexed with
alternative functions. Port 0 is the only port with no
multiplexed alternative functions. Port 3 and a part of
Port 1 are multiplexed with analog functions. Every port bit
can be independently configured in 4 different modes.
6.4.1
P
ORT FUNCTIONALITY
Port 0 8-bit bidirectional I/O port with no alternative
functions. Every port pin can be used as
open-drain, standard port, high-impedance input or
push-pull output. Port 0 is used during emulation
mode.
Port 1 8-bitbidirectionalI/O portwithalternativefunctions.
Every port, except P1.6 and P1.7 can be used as
open-drain, standard port, high-impedance input or
push-pull output.
P1.0 to P1.7 provides the inputs for the external
interrupts INT2 to INT9; the interrupts are
enabled by selecting the proper bit in the
interrupts enable register
P1.1 and P1.2 provide the Timer 2 external
trigger input (T2EX) and the Timer 2 external
count input (T2)
P1.4 provides the clock output CLKOUT
(f
psc
or f
per
)
P1.5 provide the Timer 2 clock output of the
clock-outputmode(T2OUT);toenableoutputthe
data SFR must contain logic 1s
P1.6 and P1.7 provide the I
2
C-bus clock and
data I/O, SCL and SDA. P1.6 and P1.7 can only
be configured as open-drain output or
high-impedance input; there is no clamp diode to
V
DD
. I
2
C-bus signals are connected to the port if
bit ENS1 (S1CON SFR) is set to logic 1.
Port 2 Not used.
Port 3 8-bitbidirectionalI/Oportwithalternativefunctions.
Every port can be used as open-drain, standard
port, high-impedance input or push-pull output.
P3.0 to P3.2 provide the MSK output signals
MOUT0, MOUT1 and MOUT2
P3.4 also provides the Timer 0 external clock
input
P3.5 also provides the Timer 1 external clock
input.
6.4.2
P
ORT
I/O
CONFIGURATION
Each port bit consists of a data latch, two configuration
latches, an output driver and an input buffer. The I/O port
configurations are determined by the settings in the port
configuration SFRs, PnCFGA and PnCFGB, where ‘n’
indicates the specific port number (0, 1, 3 and 4). The
combination of 2 bits in each of the 2 configuration SFRs
relates to the output setting for the corresponding port pin,
allowing any combination of the 4 I/O modes to be mixed
on those port pins. The port I/O configuration types are
shown in Fig.14 and described in
Sections 6.4.2.1 to 6.4.2.4.
6.4.2.1
Open-drain
Quasi-bidirectional I/O with n-channel open-drain output.
Use as an output requires the connection of an external
pull-up resistor; all pins have ESD protection diodes
against V
DD
and V
SS
, except for the I
2
C-bus pins P1.6 and
P1.7, which have no ESD protection to V
DD
.
6.4.2.2
Standard port
Quasi-bidirectional I/O with pull-up; the strong pull-up ‘p1’
is turned on for three clock (f
osc
) edges after a
LOW-to-HIGH transition in the port latch; after these three
clock edges the port is only weakly driven through ‘p2’ and
‘very weakly’ driven through ‘p3’ (see Fig.14b).
6.4.2.3
High-impedance input
This mode turns off all output drivers on a port. The pin will
not source or sink current and may be used as an
input-only pin. (see Fig.14c). In order not to increase the
current consumption the high-impedance input should not
float.
6.4.2.4
Push-pull
Output with drive capability in both polarities; under this
mode, pins can only be used as outputs (see Fig.14d).
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