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參數(shù)資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 52/88頁 |
| 文件大?。?/td> | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
52
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
The Master transmitter mode may now be entered by
setting the STA bit. The SIO1 logic will then test the
I
2
C-bus and generate a start condition as soon as the bus
becomes free. When a START condition is transmitted,
the serial interrupt flag (SI) is set, and the status code in
the Status Register (S1STA) will be 08H.
This status code must be used to vector to an interrupt
service routine that loads S1DAT with the slave address
and the data direction bit (SLA + W). The SI bit in S1CON
must then be reset before the serial transfer can continue.
When the slave address and the direction bit have been
transmitted and an acknowledgment bit has been
received, the serial interrupt flag (SI) is set again, and
a number of status codes in S1STA are possible.
The appropriate action to be taken for any of the status
codes is detailed in the table. After a repeated start
condition (state 10H), SIO1 may switch to the Master
receiver mode by loading S1DAT with SLA + R.
6.8.5.2
Master receiver mode
The first byte transmitted contains the slave address of the
transmittingdevice (7-bitSLA) andthe datadirection bit.In
this case the data direction bit (R/W) will be logic 1 (R).
Serial data is received via SDA while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an acknowledge bit is transmitted.
START and STOP conditions are output to indicate the
beginning and end of a serial transfer.
In the Master receiver mode, a number of data bytes are
received from a slave transmitter. The transfer is initialized
as in the Master transmitter mode. When the START
condition has been transmitted, the interrupt service
routine must load S1DAT with the 7-bit slave address and
the data direction bit (SLA + R). The SI bit in S1CON must
then be cleared before the serial transfer can continue.
When the slave address and the data direction bit have
been transmitted and an acknowledgment bit has been
received, the serial interrupt flag (SI) is set again, and
a number of status codes are possible in S1STA.
The appropriate action to be taken for each of the status
codes is detailed in the table.
After a repeated start condition (state 10H), SIO1 may
switch to the Master transmitter mode by loading S1DAT
with SLA + W.
6.8.5.3
Slave receiver mode
Serial data and the serial clock are received through SDA
and SCL. After each byte is received, an acknowledge bit
is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer.
Address recognition is performed by hardware after
reception of the slave address and direction bit.
In the slave receiver mode, a number of data bytes are
received from a master transmitter. To initiate the Slave
receiver mode, S1ADR must be loaded with the 7-bit slave
address to which SIO1 will respond when addressed by a
master. Also the least significant bit of S1ADR should be
set if the interface should respond to the general call
address (00H).The Serial Control Register (S1CON)
should be initialized with ENS1 and AA set and STA, STO,
and SI reset in order to enter the Slave receiver mode.
Setting the AA bit will enable the logic to acknowledge its
own slave address or the general call address and ENS1
will enable the interface.
When S1ADR and S1CON have been initialized, SIO1
waits until it is addressed by its own slave address
followedbythedatadirectionbitwhichmustbe logic 0 (W)
for SIO1 to operate in the Slave receiver mode. After its
own slave address and the W bit have been received, the
serial interrupt flag (SI) is set and a valid status code can
be read from S1DAT. This status code should be used to
vector to an interrupt service routine, and the appropriate
action to be taken for each of the status codes is detailed
in Table 66. The Slave receiver mode may also be entered
if arbitration is lost while SIO1 is in the Master mode.
If the AA bit is reset during a transfer, SIO1 will return a not
acknowledge (logic 1) to SDA after the next received data
byte. While AA is reset, SIO1 does not respond to its own
slave address or a general call address. However, the
I
2
C-bus is still monitored and address recognition may be
resumed at any time by setting AA. This means that the
AA bit may be used to temporarily isolate SIO1 from the
I
2
C-bus.
6.8.5.4
Slave transmitter mode
The first byte is received and handled as in the Slave
receiver mode. However, in this mode, the direction bit will
indicate that the transfer direction is reversed. Serial data
is transmitted via SDA while the serial clock is input
through SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer.
In the Slave transmitter mode, a number of data bytes are
transmitted to a master receiver. Data transfer is initialized
as in the Slave receiver mode. When S1ADR and S1CON
have been initialized, SIO1 waits until it is addressed by its
own slave address followed by the data direction bit which
must be logic 1 (R) for SIO1 to operate in the Slave
transmitter mode.
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