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參數(shù)資料
| 型號： | P83CL882 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 80C51 Ultra Low Power ULP telephony controller |
| 中文描述： | 80C51的超低功耗無鉛汽油電話控制器 |
| 文件頁數(shù)： | 46/88頁 |
| 文件大?。?/td> | 328K |
| 代理商： | P83CL882 |
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2001 Jun 19
46
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
6.8.1
S
ERIAL
C
ONTROL
R
EGISTER
(S1CON)
The CPU can read from and write to this 8-bit SFR. Two bits are affected by the SIO1 hardware: the SI bit is set when a
serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I
2
C-bus. The STO bit
is also cleared when ENS1 = 0. Reset initializes S1CON to 00H.
Table 57
Serial Control Register (SFR address D8H)
Table 58
Description of S1CON bits
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
BIT
SYMBOL
DESCRIPTION
7
CR2
This bit along with bits CR1 and CR0 determines the serial clock frequency when SIO is
in the Master mode; see Table 59. When CR2 = 0 the I
2
C-bus is in fast mode.
ENABLE serial I/O.
When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs
are in the high-impedance state; P1.6 and P1.7 function as open-drain ports. When
ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to
logic 1; note 1.
START flag.
When this bit is set in Slave mode, the SIO hardware checks the status of
the I
2
C-bus and generates a START condition if the bus is free or after the bus becomes
free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START
condition. ENS1 should not be used to temporarily release SIO1 from the I
2
C-bus since,
when ENS1 is reset, the I
2
C-bus status is lost. The AA flag should be used instead.
STOP flag.
When the STO bit is set while SIO1 is in a Master mode, a STOP condition
is transmitted to the I
2
C-bus. When the STOP condition is detected on the bus, the SIO1
hardware clears the STO flag. In a Slave mode, the STO flag may be set to recover from
an error condition. In this case, no STOP condition is transmitted to the I
2
C-bus.
However, the SIO1 hardware behaves as if a STOP condition has been received and
switches to the defined ‘not addressed’ Slave receiver mode. The STO flag is
automatically cleared by the hardware.
6
ENS1
5
STA
4
STO
If the STA and STO bits are both set, the STOP condition is transmitted to the I
2
C-bus if
SIO1 is in a Master mode (in a Slave mode, SIO1 generates an internal STOP condition
which is not transmitted). SIO1 then transmits a START condition. When the STO bit is
reset, no STOP condition will be generated.
SIO interrupt flag.
This flag is set, and an interrupt is generated, after any of the
following events occur:
A start condition is generated in Master mode
Own slave address has been received during AA = 1
The general call address has been received while S1ADR0 = 1 and AA = 1
A data byte has been received or transmitted in Master mode (even if arbitration is lost)
A data byte has been received or transmitted as selected slave
A STOP or START condition is received as selected slave receiver or transmitter.
If this flag is set, the I
2
C-bus is halted (by pulling down SCL). Received data is only valid
until this flag is reset.
3
SI
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