參數(shù)資料
型號： P83CL882
廠商： NXP Semiconductors N.V.
英文描述： 80C51 Ultra Low Power ULP telephony controller
中文描述： 80C51的超低功耗無鉛汽油電話控制器
文件頁數(shù)： 47/88頁
文件大?。?/td> 328K
代理商： P83CL882
2001 Jun 19
47
Philips Semiconductors
Product specification
80C51 Ultra Low Power (ULP) telephony controller
P83CL882
Note
1.
If the serial I/O is not enabled (ENS1), the clock to the serial I/O is switched off for power saving.
Table 59
Selection of the serial clock frequency in the Master mode of operation
Bit rates greater than 400 kHz are outside the specified frequency range.
2
AA
Assert acknowledge.
When this bit is set, an acknowledge (LOW level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
Own slave address is received
General call address is received (S1ADR.0 = 1)
A data byte is received while the device is programmed to be a master receiver
A data byte is received while the device is a selected slave receiver.
When SIO1 is in the addressed Slave transmitter mode, state C8H will be entered after
the last serial bit is transmitted. When SI is cleared, SIO1 leaves state C8H, enters the
not addressed Slave receiver mode, and the SDA line remains at a HIGH level. In state
C8H, the AA flag can be set again for future address recognition.
When SIO1 is in the not addressed Slave mode, its own slave address and the general
call address are ignored. Consequently, no acknowledge is returned, and a serial
interrupt is not requested. Thus, SIO1 can be temporarily released from the I
2
C-bus
while the bus status is monitored. While SIO1 is released from the bus, START and
STOP conditions are detected, and serial data is shifted in. Address recognition can be
resumed at any time by setting the AA flag. If the AA flag is set when the parts own
slave address or the general call address has been partly received, the address will be
recognized at the end of the byte transmission.
When this bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own slave address or general call address is received.
These two bits along with the CR2 bit determine the serial clock frequency when SIO is
in the Master mode; see Table 59.
1
0
CR1
CR0
CR2
CR1
CR0
f
per
DIVISOR
BIT RATE (kHz) AT f
per
3.58 MHz
4 MHz
6 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
20
30
40
80
120
160
358
179
119.33
89.5
44.75
29.83
22.38
400
200
133
100
50
33
25
(600)
300
199.5
150
75
49.5
37.5
not valid selection
BIT
SYMBOL
DESCRIPTION
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