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參數(shù)資料
| 型號： | PCI1410GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD CONTROLLERS |
| 中文描述： | PC卡控制器 |
| 文件頁數(shù)： | 115/145頁 |
| 文件大小： | 606K |
| 代理商： | PCI1410GHK |
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5–21
5.19 ExCA Card Detect and General Control Register
The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card
removal, as well as reports the status of VS1 and VS2 at the PC Card interface. See Table 5–14 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
ExCA I/O card detect and general control
Type
R
R
R/W
R/W
R
R
R/W
R
Default
X
X
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA card detect and general control
CardBus socket address + 816h; ExCA offset 16h
Read-only, Read/Write
XX00 0000b
Table 5–14. ExCA Card Detect and General Control Register
BIT
SIGNAL
TYPE
FUNCTION
7
VS2STAT
R
VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have
a default value.
0 = VS2 low
1 = VS2 high
6
VS1STAT
R
VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have
a default value.
0 = VS1 low
1 = VS1 high
5
SWCSC
R/W
Software card detect interrupt. If bit 3 (CDEN) in the ExCA card status-change-interrupt configuration
register is set (ExCA offset 05h, see Section 5.6), then writing a 1 to bit 5 causes a card-detect
card-status-change interrupt for the associated card socket. If bit 3 (CDEN) in the ExCA card
status-change-interrupt configuration register is cleared to 0 (see Section 5.6), then writing a 1 to bit 5 has
no effect. A read operation of this bit always returns 0.
4
CDRESUME
R/W
Card detect resume enable. If bit 4 is set to 1, then once a card detect change has been detected on CD1
and CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until bit 0 (card status change) in
the ExCA card status-change register is cleared (ExCA offset 04h, see Section 5.5). If this bit is a 0, then
the card detect resume functionality is disabled.
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
3–2
RSVD
R
Reserved. Bits 3 and 2 return 0s when read.
1
REGCONFIG
R/W
Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card
removal event. This bit is encoded as:
0 = No change to ExCA registers on card removal (default)
1 = Reset ExCA registers on card removal
0
RSVD
R
Reserved. Bit 0 returns 0 when read.
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