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參數(shù)資料
| 型號： | PCI1410GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD CONTROLLERS |
| 中文描述： | PC卡控制器 |
| 文件頁數(shù)： | 34/145頁 |
| 文件大?。?/td> | 606K |
| 代理商： | PCI1410GHK |
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2–20
Table 2–16. CardBus PC Card Interface Control Terminals
TERMINAL
NAME
NUMBER
PGE
I/O
DESCRIPTION
GGU
GHK
CAUDIO
B5
134
C10
I
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The
PCI1410 supports the binary audio mode and outputs a binary signal from the card to
SPKROUT.
CBLOCK
D11
103
E19
I/O
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CCD1
CCD2
L12
A4
75
137
L19
A9
I
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1
and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.
CDEVSEL
B13
107
E17
I/O
CardBus device select. The PCI1410 asserts CDEVSEL to claim a CardBus cycle as the target
device. As a CardBus initiator on the bus, the PCI1410 monitors CDEVSEL until a target
responds. If no target responds before timeout occurs, then the PCI1410 terminates the cycle
with an initiator abort.
CFRAME
B11
111
E14
I/O
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is
asserted to indicate that a bus transaction is beginning, and data transfers continue while this
signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final
data phase.
CGNT
C11
106
F15
O
CardBus bus grant. CGNT is driven by the PCI1410 to grant a CardBus PC Card access to the
CardBus bus after the current data transaction has been completed.
CINT
D6
132
A10
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing
from the host.
CIRDY
A12
110
C15
I/O
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the
current data phase of the transaction. A data phase is completed on a rising edge of CCLK when
both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted,
wait states are inserted.
CPERR
C13
104
F14
I/O
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during
special cycles. It is driven low by a target two clocks following that data when a parity error is
detected.
CREQ
B8
123
E12
I
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the
CardBus bus as an initiator.
CSERR
A5
133
B10
I
CardBus system error. CSERR reports address parity errors and other system errors that could
lead to catastrophic results. CSERR is driven by the card synchronous to CCLK. The PCI1410
can report CSERR to the system by assertion of SERR on the PCI interface.
CSTOP
C12
105
E18
I/O
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current
CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by
target devices that do not support burst data transfers.
CSTSCHG
C5
135
E10
I
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is
used as a wake-up mechanism.
CTRDY
A13
109
A16
I/O
CardBus target ready. CTRDY indicates the ability of the CardBus target ability to complete the
current data phase of the transaction. A data phase is completed on a rising edge of CCLK,
when both CIRDY and CTRDY are asserted; until this time, wait states are inserted.
CVS1
CVS2
C6
D9
131
117
F11
E13
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in
conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine
the operating voltage and card type.
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