![](http://datasheet.mmic.net.cn/330000/PCI1410GHK_datasheet_16443868/PCI1410GHK_49.png)
3–15
To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be
programmed with the byte address, and the serial bus slave address register must be programmed with the 7-bit slave
address (SLAVADDR field) and bit 0 (RWCMD) must be reset.
On byte reads, the byte address is programmed into the serial bus index register, he serial bus slave address register
must be programmed with the 7-bit slave address (SLAVADDR field) and bit 0 (RWCMD) must be set, and bit 5
(REQBUSY) in the serial bus control and status register (see Section 4.50) must be polled until clear. Then the
contents of the serial bus data register are valid read data from the serial bus interface.
3.7
Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
PCI1410. The PCI1410 provides several interrupt signaling schemes to accommodate the needs of a variety of
platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and
industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the
CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1410 is, therefore,
backward compatible with existing interrupt control register definitions, and new registers have been defined where
required.
The PCI1410 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using
one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1410, PC Card interrupts
are classified as either card status change (CSC) or as functional interrupts.
The method by which any type of PCI1410 interrupt is communicated to the host interrupt controller varies from
system to system. The PCI1410 offers system designers the choice of using parallel PCI interrupt signaling, parallel
ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the
parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that
follow. All interrupt signalling is provided through the seven multifunction terminals, MFUNC0–MFUNC6.
3.7.1
PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the
PCI1410 and may warrant notification of host card and socket services software for service. CSC events include both
card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.
Table 3–8 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards
that can be inserted into any PC Card socket are:
16-bit memory card
16-bit I/O card
CardBus cards