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參數(shù)資料
| 型號： | PCI1410GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD CONTROLLERS |
| 中文描述： | PC卡控制器 |
| 文件頁數(shù)： | 32/145頁 |
| 文件大?。?/td> | 606K |
| 代理商： | PCI1410GHK |
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2–18
Table 2–13. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
NAME
NUMBER
I/O
DESCRIPTION
GGU
PGE
GHK
READY
(IREQ)
D6
132
A10
I
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket
are configured for the memory-only interface. READY is driven low by the 16-bit memory PC
Cards to indicate that the memory card circuits are busy processing a previous write command.
READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer
command.
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device
on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when
no interrupt is requested.
REG
B7
125
B12
O
Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or
IOWR active). Attribute memory is a separately accessed section of card memory and is generally
used to record card capacity and other configuration and attribute information.
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a
16-bit PC Card that supports DMA. The PCI1410 asserts REG to indicate a DMA operation. REG
is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.
RESET
B9
119
F12
O
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
VS1
VS2
C6
D9
131
117
F11
E13
I/O
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,
determine the operating voltage of the PC Card.
WAIT
A5
133
B10
I
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or
I/O cycle in progress.
WE
C11
106
F15
O
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also
used for memory PC Cards that employ programmable memory technologies.
DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports
DMA. The PCI1410 asserts WE to indicate TC for a DMA read operation.
WP
(IOIS16)
D5
136
F10
I
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16)
function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card
when the address on the bus corresponds to an address to which the 16-bit PC Card responds,
and the I/O port that is addressed is capable of 16-bit accesses.
DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA
operation.
Table 2–14. CardBus PC Card Interface System Terminals
TERMINAL
NAME
NUMBER
PGE
I/O
DESCRIPTION
GGU
GHK
CCLK
B12
108
D19
O
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface.
All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and
CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the
rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped
in the low state or slowed down for power savings.
CCLKRUN
D5
136
F10
I/O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK
frequency, and by the PCI1410 to indicate that the CCLK frequency is going to be decreased.
CRST
B9
119
F12
O
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a
known state. When CRST is asserted, all CardBus PC Card signals are placed in a
high-impedance state, and the PCI1410 drives these signals to a valid logic level. Assertion can
be asynchronous to CCLK, but deassertion must be synchronous to CCLK.
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