參數(shù)資料
型號： PCI1410GHK
廠商： Texas Instruments, Inc.
英文描述： PC CARD CONTROLLERS
中文描述： PC卡控制器
文件頁數(shù)： 28/145頁
文件大?。?/td> 606K
代理商： PCI1410GHK
2–14
Table 2–10. PCI Interface Control Terminals
TERMINAL
NAME
NUMBER
PGE
I/O
DESCRIPTION
GGU
GHK
DEVSEL
L1
32
P6
I/O
PCI device select. The PCI1410 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI
initiator on the bus, the PCI1410 monitors DEVSEL until a target responds. If no target responds
before timeout occurs, then the PCI1410 terminates the cycle with an initiator abort.
FRAME
J4
28
P2
I/O
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that
a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME
is deasserted, the PCI bus transaction is in the final data phase.
GNT
B1
2
H1
I
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1410 access to the PCI bus after
the current data transaction has completed. GNT may or may not follow a PCI bus request, depending
on the PCI bus parking algorithm.
IDSEL
F4
13
L1
I
Initialization device select. IDSEL selects the PCI1410 during configuration space accesses. IDSEL
can be connected to one of the upper 24 PCI address lines on the PCI bus.
IRDY
K1
29
N5
I/O
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase
of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY
are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.
PERR
L3
34
P5
I/O
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not
match PAR when PERR is enabled through bit 6 of the command register (offset 04h, see
Section 4.4).
REQ
A1
1
H2
O
PCI bus request. REQ is asserted by the PCI1410 to request access to the PCI bus as an initiator.
SERR
M1
35
R3
O
PCI system error. SERR is an output that is pulsed from the PCI1410 when enabled through bit 8 of
the command register (offset 04h, see Section 4.4) indicating a system error has occurred. The
PCI1410 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the
command register, this signal also pulses, indicating that an address parity error has occurred on a
CardBus interface.
STOP
L2
33
R2
I/O
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI
bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that
do not support burst data transfers.
TRDY
K3
31
R1
I/O
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data
phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and
TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.
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