![](http://datasheet.mmic.net.cn/330000/PCI1410GHK_datasheet_16443868/PCI1410GHK_42.png)
3–8
Speaker
Subsystem
BINARY_SPKR
System
Core Logic
PCI1410
CAUDPWM
SPKROUT
PWM_SPKR
Figure 3–7. Sample Application of SPKROUT and CAUDPWM
3.5.8
LED Socket Activity Indicators
The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LED_SKT signal can be
routed to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to
indicate socket activity. See Section 4.30, Multifunction Routing Register
for details on configuring the multifunction
terminals.
The LED signal is active high and is driven in pulses of 64-ms duration. When the LED is not being driven high, it is
driven to a low state. Either of the two circuits shown in Figure 3–8 can be implemented to provide LED signaling and
it is left for the board designer to implement the circuit that best fits the application.
The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity
signal is pulsed when READY/IREQ is low. For CardBus cards, the LED activity signal is pulsed if CFRAME, CIRDY,
or CREQ is active.
PCI1410
Application-
Specific Delay
Current Limiting
R
≈
500
PCI1410
Current Limiting
R
≈
500
LED
LED
Figure 3–8. Two Sample LED Circuits
As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LED
appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is
asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), then the LED signal remains driven.
3.5.9
PC Card-16 Distributed DMA Support
The PCI1410 supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA)
slave register set provides the programmability necessary for the slave DDMA engine. Table 3–2 provides the DDMA
register configuration.