參數(shù)資料
型號(hào)： PI7C8150BMAE
廠商： Pericom
文件頁(yè)數(shù)： 100/109頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 208-FQFP
標(biāo)準(zhǔn)包裝： 24
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-FQFP（28x28）
包裝： 管件
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 1227 (CN2011-ZH PDF)
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 90 of 109
April 2009 – Revision 1.08
14.1.39
GPIO DATA AND CONTROL REGISTER – OFFSET 64h
Bit
Function
Type
Description
11:8
GPIO Output
Write-1-to-Clear
R/WC
Writing 1 to any of these bits drives the corresponding bit LOW on
the GPIO[3:0] bus if it is programmed as bidirectional. Data is
driven on the PCI clock cycle following completion of the
configuration write to this register. Bit positions corresponding to
GPIO pins that are programmed as input only are not driven. Writing
0 has no effect and will show last the last value written when read.
Reset to 0.
15:12
GPIO Output
Write-1-to-Set
R/WS
Writing 1 to any of these bits drives the corresponding bit HIGH on
the GPIO[3:0] bus if it is programmed as bidirectional. Data is
driven on the PCI clock cycle following completion of the
configuration write to this register. Bit positions corresponding to
GPIO pins that are programmed as input only are not driven. Writing
0 has no effect and will show last the last value written when read.
Reset to 0.
19:16
GPIO Output
Enable Write-1-
to-Clear
R/WC
Writing 1 to and of these bits configures the corresponding
GPIO[3:0] pin as an input only. The output driver is tristated.
Writing 0 to this register has no effect and will reflect the last value
written when read.
Reset to 0.
23:20
GPIO Output
Enable Write-1-
to-Set
R/WS
Writing 1 to and of these bits configures the corresponding
GPIO[3:0] pin as bidirectional. The output driver is enabled and
drives the value set in the output data register (65h). Writing 0 to this
register has no effect and will reflect the last value written when read.
Reset to 0.
27:24
Reserved
R
Reserved. Returns 0 when read. Reset to 0.
31:28
GPIO Input Data
Register
R/O
Reads the state of the GPIO[3:0] pins. The state is updated on the PCI
clock following a change in the GPIO[3:0] pins.
14.1.40
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
Bit
Function
Type
Description
1:0
Clock 0 disable
R/W
If either bit is 0, then S_CLKOUT [0] is enabled.
If both bits are 1, then S_CLKOUT [0] is disabled.
3:2
Clock 1 disable
R/W
If either bit is 0, then S_CLKOUT [1] is enabled.
If both bits are 1, then S_CLKOUT [1] is disabled.
5:4
Clock 2 disable
R/W
If either bit is 0, then S_CLKOUT [2] is enabled.
If both bits are 1, then S_CLKOUT [2] is disabled.
7:6
Clock 3 disable
R/W
If either bit is 0, then S_CLKOUT [3] is enabled.
If both bits are 1, then S_CLKOUT [3] is disabled.
8
Clock 4 disable
R/W
If bit is 0, then S_CLKOUT [4] is enabled.
If bit is 1, then S_CLKOUT [4] is disabled and driven low.
9
Clock 5 disable
R/W
If bit is 0, then S_CLKOUT [5] is enabled.
If bit is 1, then S_CLKOUT [5] is disabled and driven low.
10
Clock 6 disable
R/W
If bit is 0, then S_CLKOUT [6] is enabled.
If bit is 1, then S_CLKOUT [6] is disabled and driven low.
11
Clock 7 disable
R/W
If bit is 0, then S_CLKOUT [7] is enabled.
If bit is 1, then S_CLKOUT [7] is disabled and driven low.
12
Clock 8 disable
R/W
If bit is 0, then S_CLKOUT [8] is enabled.
If bit is 1, then S_CLKOUT [8] is disabled and driven low.
13
Clock 9 disable
R/W
If bit is 0, then S_CLKOUT [9] is enabled.
If bit is 1, then S_CLKOUT [9] is disabled and driven low.
15:14
Reserved
RO
Reserved. Returns 00 when read.
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