參數(shù)資料
型號(hào): PI7C8150BMAE
廠商: Pericom
文件頁數(shù): 25/109頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 208-FQFP
標(biāo)準(zhǔn)包裝: 24
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-FQFP(28x28)
包裝: 管件
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1227 (CN2011-ZH PDF)
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 22 of 109
April 2009 – Revision 1.08
3
This Chapter offers information about PCI transactions, transaction forwarding across
PI7C8150B, and transaction termination. The PI7C8150B has two 128-byte FIFO’s for
buffering of upstream and downstream transactions. These hold addresses, data,
commands, and byte enables that are used for write transactions. The PI7C8150B also has
an additional four 128-byte FIFO’s that hold addresses, data, commands, and byte enables
for read transactions.
3.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8150B.
Table 3-1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C8150B initiates
transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150B
responds to transactions as a target, on the primary (P) and secondary (S) buses.
Table 3-1. PCI Transactions
Types of Transactions
Initiates as Master
Responds as Target
Primary
Secondary
Primary
Secondary
0000
Interrupt Acknowledge
N
0001
Special Cycle
Y
N
0010
I/O Read
Y
0011
I/O Write
Y
0100
Reserved
N
0101
Reserved
N
0110
Memory Read
Y
0111
Memory Write
Y
1000
Reserved
N
1001
Reserved
N
1010
Configuration Read
N
Y
N
1011
Configuration Write
Y (Type 1 only)
Y
Y (Type 1 only)
1100
Memory Read Multiple
Y
1101
Dual Address Cycle
Y
1110
Memory Read Line
Y
1111
Memory Write and Invalidate
Y
As indicated in Table 3-1, the following PCI commands are not supported by
PI7C8150B:
PI7C8150B never initiates a PCI transaction with a reserved command code and, as a
target, PI7C8150B ignores reserved command codes.
PI7C8150B does not generate interrupt acknowledge transactions. PI7C8150B
ignores interrupt acknowledge transactions as a target.
PI7C8150B does not respond to special cycle transactions. PI7C8150B cannot
guarantee delivery of a special cycle transaction to downstream buses because of the
broadcast nature of the special cycle command and the inability to control the
transaction as a target. To generate special cycle transactions on other PCI buses,
either upstream or downstream, Type 1 configuration write must be used.
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