參數(shù)資料
型號(hào)： PI7C8150BMAE
廠商： Pericom
文件頁(yè)數(shù)： 41/109頁(yè)
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 208-FQFP
標(biāo)準(zhǔn)包裝： 24
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-FQFP（28x28）
包裝： 管件
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 1227 (CN2011-ZH PDF)
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 37 of 109
April 2009 – Revision 1.08
Target disconnect
Target abort
PI7C8150B handles these terminations in different ways, depending on the type of
transaction being performed.
3.8.3.1
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8150B initiates a delayed write transaction, the type of target termination
received from the target can be passed back to the initiator. Table 3-7 shows the response
to each type of target termination that occurs during a delayed write transaction.
PI7C8150B repeats a delayed write transaction until one of the following conditions is met:
PI7C8150B completes at least one data transfer.
PI7C8150B receives a master abort.
PI7C8150B receives a target abort.
PI7C8150B makes 2
24 (default) or 232 (maximum) write attempts resulting in a response of
target retry.
Table 3-7. Delayed Write Target Termination Response
Target Termination
Response
Normal
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Target Retry
Returning target retry to initiator. Continue write attempts to target
Target Disconnect
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Target Abort
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
After the PI7C8150B makes 2
24 (default) attempts of the same delayed write trans-action
on the target bus, PI7C8150B asserts P_SERR_L if the SERR_L enable bit (bit 8 of
command register for the secondary bus) is set and the delayed-write-non-delivery bit is
not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register
(offset 64h). PI7C8150B will report system error. See Section 6.4 for a description of
system error conditions.
3.8.3.2
POSTED WRITE TARGET TERMINATION RESPONSE
When PI7C8150B initiates a posted write transaction, the target termination cannot be
passed back to the initiator. Table 3-8 shows the response to each type of target
termination that occurs during a posted write transaction.
Table 3-8. Response to Posted Write Target Termination
Target Termination
Repsonse
Normal
No additional action.
Target Retry
Repeating write transaction to target.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150BMAI 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
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