參數(shù)資料
型號: PI7C8150BMAE
廠商: Pericom
文件頁數(shù): 95/109頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 208-FQFP
標(biāo)準(zhǔn)包裝: 24
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-FQFP(28x28)
包裝: 管件
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1227 (CN2011-ZH PDF)
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 86 of 109
April 2009 – Revision 1.08
Bit
Function
Type
Description
4
Secondary Bus
Prefetch Disable
R/W
Controls the bridge’s ability to prefetch during upstream memory
read transactions.
0: The bridge prefetches and does not forward byte enable bits during
upstream memory reads.
1: The bridge requests only 1 DWORD from the target and forwards
read byte enable bits during upstream memory reads.
Reset to 0
5
Live Insertion
Mode
R/W
Enables hardware control of transaction forwarding.
0: GPIO[3] has no effect on the I/O, memory, and master enable bits
1: If GPIO[3] is set to input mode, this bit enables GPIO[3] to mask
I/O enable, memory enable and master enable bits to 0. PI7C8150B
will stop accepting I/O and memory transactions as a result.
Reset to 0
7:6
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
8
Chip Reset
R/WR
Controls the chip and secondary bus reset.
0: PI7C8150B is ready for operation
1: Causes PI7C8150B to perform a chip reset
10:9
Test Mode For
All Counters at P
and S1
R/O
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
00: all bits are exercised
01: byte 1 is exercised
10: byte 2 is exercised
11: byte 3 is exercised
Reset to 0
15:11
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
14.1.30
ARBITER CONTROL REGISTER – OFFSET 40h
Bit
Function
Type
Description
24:16
Arbiter Control
R/W
Each bit controls whether a secondary bus master is assigned to the
high priority group or the low priority group.
Bits [24:16] correspond to request inputs S_REQ_L[8:0]
respectively.
Bit 24 corresponds to S_REQ_L[8]
Bit 16 corresponds to S_REQ_L[0]
0: low priority
1: high priority
Reset to 0
25
Priority of
Secondary
Interface
R/W
Controls whether the secondary interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 1
31:26
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
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