參數(shù)資料
型號： PI7C8150BMAE
廠商： Pericom
文件頁數(shù)： 56/109頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 208-FQFP
標(biāo)準(zhǔn)包裝： 24
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-FQFP（28x28）
包裝： 管件
安裝類型： 表面貼裝
產(chǎn)品目錄頁面： 1227 (CN2011-ZH PDF)
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 50 of 109
April 2009 – Revision 1.08
read operation, either from the device to the location just written (or some other location
along the same path), or from the device driver to one of the device registers.
6
ERROR HANDLING
PI7C8150B checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C8150B always tries to forward the existing
parity condition on one bus to the other bus, along with address and data. PI7C8150B
always attempts to be transparent when reporting errors, but this is not always possible,
given the presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C8150B implements the following:
PERR_L and SERR_L signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR_L event disable register
This chapter provides detailed information about how PI7C8150B handles errors.
It also describes error status reporting and error operation disabling.
6.1
ADDRESS PARITY ERRORS
PI7C8150B checks address parity for all transactions on both buses, for all address and all
bus commands. When PI7C8150B detects an address parity error on the primary interface,
the following events occur:
If the parity error response bit is set in the command register, PI7C8150B does not
claim the transaction with P_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally
and accepts the transaction if it is directed to or across PI7C8150B.
PI7C8150B sets the detected parity error bit in the status register.
PI7C8150B asserts P_SERR_L and sets signaled system error bit in the status register,
if both the following conditions are met:
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the command register.
When PI7C8150B detects an address parity error on the secondary interface, the following
events occur:
If the parity error response bit is set in the bridge control register, PI7C8150B does not
claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally
and accepts transaction if it is directed to or across PI7C8150B.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150BMAI 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMAI-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMAIE 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BMAIE-33 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BND 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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