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參數(shù)資料
| 型號： | PI7C8150BMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 93/109頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 208-FQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-FQFP（28x28） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 1227 (CN2011-ZH PDF) |
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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 84 of 109
April 2009 – Revision 1.08
14.1.27
INTERRUPT PIN REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
15:8
Interrupt Pin
R/O
Interrupt pin not supported on the PI7C8150B
14.1.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
16
Parity Error
Response
R/W
Controls the bridge’s response to parity errors on the secondary
interface.
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary
interface
Reset to 0
17
S_SERR_L
enable
R/W
Controls the forwarding of S_SERR_L to the primary interface.
0: disable the forwarding of S_SERR_L to primary interface
1: enable the forwarding of S_SERR_L to primary interface
Reset to 0
18
ISA enable
R/W
Modifies the bridge’s response to ISA I/O addresses, applying only
to those addresses falling within the I/O base and limit address
registers and within the first 64KB or PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and
I/O limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the
I/O base and I/O limit registers that are in the first 64KB of I/O space
that address the last 768 bytes in each 1KB block. Secondary I/O
transactions are forwarded upstream if the address falls within the
last 768 bytes in each 1KB block
Reset to 0
19
VGA enable
R/W
Controls the bridge’s response to VGA compatible addresses.
0: does not forward VGA compatible memory and I/O addresses
from primary to secondary
1: forward VGA compatible memory and I/O addresses from primary
to secondary regardless of other settings
Reset to 0
20
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
21
Master Abort
Mode
R/W
Control’s bridge’s behavior responding to master aborts on
secondary interface.
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible by the
assertion of P_SERR_L if enabled
Reset to 0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150BMAI | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMAI-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMAIE | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150BMAIE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150BND | 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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