參數(shù)資料
型號： PM7351-BI
廠商： PMC-SIERRA INC
元件分類： 數(shù)字傳輸電路
英文描述： OCTAL SERIAL LINK MULTIPLEXER
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA304
封裝： 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304
文件頁數(shù)： 137/174頁
文件大?。?/td> 1790K
代理商： PM7351-BI
RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
127
12
OPERATION
This section complements Section 9 Functional Description, by describing in
greater detail some of the programming and cross-functional issues that a
designer using the S/UNI-VORTEX may want to consider.
12.1 Determining the Value for FREADY[5:0]
As discussed in Section 9.1.1, a downstream cell transfer should be initiated only
after polling the appropriate downstream channel and ensuring that the buffer is
empty, as indicated by that channel’s TPA (Transmit Packet Available) output
being asserted. The cell buffer status for each downstream channel (i.e. the
status that will be driven onto the TPA output when the channel is polled) is
deasserted when the first byte of a cell is written into the buffer. It is re-asserted
only after the number of bytes programmed into the FREADY[5:0] field of the
associated Downstream Logical Channel FIFO Ready Level register have been
serialized onto a high-speed link. Determining whether or not it is necessary for
you to adjust the default value of FREADY[5:0] is discussed in this section.
Each S/UNI-VORTEX has a total of 264 downstream cell buffers. There are 33
buffers per LVDS link (32 PHYs plus the microprocessor port), and 8 links in
total. Each link is independent of, but identical to the others, so we need only
describe how a single link works for you to understand how all downstream links
function.
At the end of each cell transfer on the LVDS link the downstream scheduler polls
(round-robin) its 33 buffers looking for the next buffer with a whole cell to send
(the scheduler ignores buffers that are in the process of having a cell written to
them). If there is no cell to send the scheduler immediately injects a stuff cell on
the link. Once the link starts sending out the cell from a buffer, the entire cell will
be sent before the scheduler begins its next scheduling cycle. Since a buffer
cannot have more than one cell stored in it at a time, no single downstream
channel can ever operate at a bandwidth greater than the bandwidth of the
LVDS link. Even if there are no other channels active, the scheduler will inject a
stuff cell before the next cell from the same channel is available.
So what does this mean to the system designer The maximum
per channel
bandwidth (i.e. the LVDS line rate) will only be sustained if the bus master
always writes the next cell into the downstream buffer within the time it takes to
transmit a single cell over the LVDS link. Since the system bus is normally
running much faster than the LVDS link this is not a problem in most designs.
However, there are two scenarios in which the designer may be concerned about
the time delay between TPA asserted and the last byte of the cell being written
into the buffer:
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