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參數(shù)資料
| 型號： | PM7351-BI |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OCTAL SERIAL LINK MULTIPLEXER |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA304 |
| 封裝： | 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304 |
| 文件頁數(shù)： | 139/174頁 |
| 文件大?。?/td> | 1790K |
| 代理商： | PM7351-BI |
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RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
129
been sent out on the LVDS link. If FREADY is set to a value less than the
cell length then TPA will be asserted in advance of the buffer being
completely empty.
5. The bus master can use this advanced TPA signal to shorten the time until
the next cell is fully written into the buffer. The bus master can initiate the
write of the next cell anytime after TPA is asserted. However, under no
circumstances should the bus master complete the write of the full cell
before the current cell is serialized and sent out on the LVDS link. Doing
so will result in buffer overflow and data corruption.
6. Starting the write of the next cell while there is still a few bytes remaining
from the previous cell does not impact how the FREADY value is used.
The counter that tracks the number of bytes serialized from each cell will
not be reset until the previous cell has left the buffer. In other words,
when determining the value of the FIFO Ready Level you can ignore the
fact that cell writes can be partially overlapped.
From the above discussion it is clear that reducing the value of FREADY[5:0]
from its default value of 50 must be done carefully. A value of 50 or greater will
never result in buffer overflow even under worse case conditions, which are:
bus running at 800 Mbps,
LVDS link running at 100 Mbps
Since word 0 is stripped from the cell before it is stored in the downstream buffer,
the longest cell stored in the buffer is 56 bytes (this assumes the optional user
prepend is enabled). In the worse case scenario the LVDS link is running 8
times slower than the system bus, which means in the time it takes to send the
remaining 6 bytes out on the LVDS link there will at most be 48 bytes written into
the buffer via the system bus. Since this is less than the cell length overflow
cannot occur if FREADY[5:0] is left at its default value.
If your system design is such that your downstream PHYs are operating near the
maximum supported rate ( the LVDS line rate) and your system bus is less
than the maximum you may want to advance the TPA signal by reducing
FREADY[5:0]. The closer to the LVDS line rate the system bus is running, the
lower FREADY[5:0] can be set. To determine the minimum value for
FREADY[5:0] you must take into account the ratio between the LVDS link rate
and the Any-PHY bus rate. You should also take into account the minimum
latency between TPA asserted and the bus master starting the next write cycle.
FREADY[5:0] should not be set lower than 9 for the reasons discussed
previously.
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