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參數(shù)資料
| 型號(hào)： | PM7351-BI |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OCTAL SERIAL LINK MULTIPLEXER |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA304 |
| 封裝： | 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304 |
| 文件頁數(shù)： | 20/174頁 |
| 文件大小： | 1790K |
| 代理商： | PM7351-BI |
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RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
10
6
DESCRIPTION
The PM7351 S/UNI-VORTEX is a monolithic integrated circuit typically used with
its sister device, the S/UNI-DUPLEX, to implement a point-to-point serial
backplane interconnect architecture.
Up to sixteen S/UNI-VORTEX devices can reside on a common cell processing
card along side a traffic management device. The traffic management device
exchanges cells with the S/UNI-VORTEX via 16-bit SCI-PHY or Any-PHY
interfaces. Flow control is effected across this interface via cell available signals
generated by the S/UNI-VORTEX. In the downstream direction, the availability
of a buffer for each logical channel can be polled by the traffic management
device. In the upstream direction, an indication is provided whether there is one
or more cells queued in the S/UNI-VORTEX for transfer.
Each S/UNI-VORTEX can be connected to eight line cards via 100 to 200 Mb/s
serial links. Each upstream link has its own queue. If a queue becomes nearly
full, a flow control indication is sent downstream. In the downstream direction,
each logical channel has a dedicated cell buffer to avoid head of line blocking.
The serialization of cells from the cell buffers is throttled by flow control
information sent from the line card via the upstream high-speed link.
A microprocessor port provides access to internal configuration and monitoring
registers. The port may also be used to insert and extract cells in support of a
control channel.
LVDS INTERFACES, BOTH DIRECTIONS
8 independent 4-wire LVDS serial transceivers each operating at up to 200
Mbps across PCB or backplane traces, or across up to 10 meters of 4-wire
twisted pair cabling for inter-shelf communications.
Usable bandwidth (excludes system overhead) of 186 Mbps per direction per
LVDS link.
Full integrated LVDS clock synthesis and recovery. No external analog
components are required.
LVDS RECEIVE DIRECTION
Weighted round robin multiplex of cell streams from the 8 LVDS links into a
single cell stream which is transferred to the parallel bus under control of the
bus master.
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