參數(shù)資料
型號： PM7351-BI
廠商： PMC-SIERRA INC
元件分類： 數(shù)字傳輸電路
英文描述： OCTAL SERIAL LINK MULTIPLEXER
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA304
封裝： 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304
文件頁數(shù)： 144/174頁
文件大?。?/td> 1790K
代理商： PM7351-BI
RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
134
Near end
downstream
Reg 0x0008
Far-end
upstream
Reg 0x00C
LVDS:
both ends
must match
e.g. Reg
0x080 and
0x90
U
S
R
H
D
R
N
D
Resultant Cell contents at far-end Bus or Microprocessor
H
5
U
D
F
I
N
A
D
D
U
D
F
P
R
E
P
E
N
D
H
5
U
D
F
I
N
A
D
D
U
D
F
P
R
E
P
E
N
D
P
R
E
P
E
C
E
L
L
C
R
C
Note: USRHDR is a two bit value that defines the number of
header bytes transferred over the LVDS link.
00 = 4 bytes
01 = 5 bytes (UDF not sent)
10 = 6 bytes (default)
11 = reserved
Note: The LVDS transmitter adds 5 overhead bytes to every
cell, which includes room for PHY address information. Thus
the LVDS cell format is the same whether the PHY address
arrives as a prepend or embedded in the H5/UDF field.
first byte the prepend is undefined, the second byte
contains the CRC8 from the previous cell. H5/UDF is
undefined.
Control cell prepend byte 2 is carried as is, but prepend
byte 3 is overwritten with the CRC8. Header bytes 8&9
are undefined.
THIS CONFIGURATION NOT VALID IF RANYPHY = 1
56 byte cells (5 system, 2 CRC, 4 header bytes) are
transferred from a 54 byte bus to a 54 byte bus.
At far-end the H5/UDF fields contains the PHY address.
There is no prepend.
Control cell prepend bytes 2 is carried as is. Prepend
byte 3 is overwritten with the CRC8. Header bytes 8&9
are undefined.
X
1
0
X
1
0
4
1
1
.
12.3 Minimum Programming
Besides the bus configuration described in the previous section, very little
configuration is required to make the part function. As an absolute minimum the
following registers must be written before any cell traffic is possible:
1. Logical Channel Base Address registers (0x08A, 0x0AA, 0x0CA, 0x0EA,
0x10A, 0x12A, 0x14A and 0x16A) and Logical Channel Address
Range/Logical Channel Base Address MSB registers (0x08B, 0x0AB,
0x0CB, 0x0EB, 0x10B, 0x12B, 0x14B and 0x16B) - These registers map
the eight LVDS links into the 4096 channel address space of the
downstream Any-PHY bus. The address mapping must match the
configuration of the bus master.
2. Control Channel Base Address register (0x005) and Control Channel
Base Address MSB register (0x006) – These registers determine the
location of the eight control channels within the address space of the
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