參數(shù)資料
型號： PM7351-BI
廠商： PMC-SIERRA INC
元件分類： 數(shù)字傳輸電路
英文描述： OCTAL SERIAL LINK MULTIPLEXER
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA304
封裝： 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304
文件頁數(shù)： 151/174頁
文件大?。?/td> 1790K
代理商： PM7351-BI
RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
141
STCTEST
The single transport chain instruction is used to test out the TAP controller and
the boundary scan register during production test. When this instruction is the
current instruction, the boundary scan register is connected between TDI and
TDO. During the Capture-DR state, the device identification code is loaded into
the boundary scan register. The code can then be shifted out output, TDO using
the Shift-DR state.
12.5 Microprocessor Inband Communication
Control channel cells can be inserted and extracted through the parallel
microprocessor interface. In both the upstream and downstream directions,
each high-speed serial link has a dedicated queue for the control channel cells.
Although the interface is based on cell-at-a-time transfers, the goal is to provide
efficient transmission and reception of packets of information. The
microprocessor will have to perform the packet segmentation and reassembly
function, but the S/UNI-VORTEX includes hardware support for CRC-32
generation and verification. It consists of two accumulator registers: the Insert
CRC-32 Accumulator register for the downstream direction and the Extract CRC-
32 Accumulator for control channel in the upstream direction.
To allow context change
1
, each accumulator register can be preset, read and
written by the microprocessor.
12.5.1 Inserting Cells Into Control Channels
Cells are inserted into control channels by manipulating the Microprocessor
Insert FIFO Control and Microprocessor Insert FIFO Ready registers. The
following steps are required to insert a cell:
1. Poll the INSRDY[7:0] bits in the Microprocessor Insert FIFO Ready register.
Alternately, service the interrupts that result from setting the INSRDYE bit in
the Microprocessor Cell Buffer Interrupt Control and Status register.
2. If a multi-cell CRC-32 calculation is required set the INSCRCPR of the
Microprocessor Insert FIFO Control register to logic 0 to enable the CRC-32
process. The Insert CRC-32 Accumulation register can be preset by writing a
logic 1 to INSCRCPR prior to enabling the CRC-32 calculation.
1
A context change is, for example, when you are in the middle of sending a multi-cell packet on LVDS link
A when a high priority event causes you to want to interrupt the packet transfer and send a packet out on
link B. You would complete the current cell write to Link A, save the partial CRC, switch links, send the
cells for link B, switch back to link A, reload the partial CRC and continue with the rest of link A’s packet.
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