參數(shù)資料
型號： PM7351-BI
廠商： PMC-SIERRA INC
元件分類： 數(shù)字傳輸電路
英文描述： OCTAL SERIAL LINK MULTIPLEXER
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA304
封裝： 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304
文件頁數(shù)： 58/174頁
文件大?。?/td> 1790K
代理商： PM7351-BI
RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
48
link is throttled by the UPCA bit in the upstream cell prepends. The UPCA bit
reflects the buffer availability on the line card.
In the downstream direction, the control channels for the eight links are provided
with a polling address range set by the Control Channel Base Address register.
As discussed in Section 9.1.1, the TPA status for each control channel can be
discovered by presenting a TADR[11:0] value in the specified range. A
transferred control channel cell is accepted when the ADDR[11:0] field in the cell
structure corresponds to one of the eight addresses specified by the Control
Channel Base Address register.
In the upstream direction, control channel cells are given no special treatment
when they are directed to the upstream SCI-PHY/Any-PHY bus. The traffic
management device can identify them by an encoding of “111110” in the
ADDR[5:0] field in the cell prepend or H5.UDF field.
9.6.3 Insertion and Extraction Via the Micro-Processor Interface
Control cells can be inserted and extracted through the parallel microprocessor
interface.
9.6.3.1 Writing Cells
The S/UNI-VORTEX contains a two cell buffer per high-speed link for the
insertion of a cell by the microprocessor onto the high-speed serial links.
Optional CRC-32 calculation over the last 48 bytes of the cell relieves the
microprocessor of this task. The CRC-32 generator polynomial is consistent with
AAL5:
G(x) = x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+x
5
+ x
4
+x
2
+ x + 1
All cells written by the microprocessor will have binary 111110 encoded in the
PHYID[5:0] field within the cell prepend bytes. This distinction between user
cells and control cells provides a clear channel for both types of cells. The
microprocessor cell format is illustrated in Fig. 7. The 8-bit cell data structure is
fixed at 60 bytes long regardless of how the SCI-PHY/Any-PHY bus and LVDS
link are configured. The microprocessor must transfer all bytes of the cell,
including the unused ones. The unused bytes are included in the received cell
when it is made available to the far-end microprocessor, but the value of the
bytes is undefined.
Bytes marked with an asterisk in Fig. 7 must be included in cells written into the
cell transfer register, but they will only be sent across the LVDS if the
corresponding Transmit High-Speed Serial Configuration register and the far-
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