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參數(shù)資料
| 型號(hào)： | PM7351-BI |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OCTAL SERIAL LINK MULTIPLEXER |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA304 |
| 封裝： | 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304 |
| 文件頁(yè)數(shù)： | 41/174頁(yè) |
| 文件大?。?/td> | 1790K |
| 代理商： | PM7351-BI |
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RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
31
4. The H5/UDF fields contain the ADDR[11:0] value and are used to route
transferred cells. In this case Word 0 is not used and should not
generated by the bus master.
The treatment of the H5/UDF field, the address prepend(word 0), and their
corresponding fields on the LVDS link are independent of that of the User
Prepend. See Section 12.2 Interaction Between Bus and LVDS Configurations
on page 130 for further details.
Although the ability to carry the inband address in the H5/UDF fields is provided
for compatibility with devices that cannot generate an address prepend, there are
two constraints that must be respected in this configuration:
1. Recall that in the default case (i.e. Word 0 provides the address) the
logical channel participating in a cell transfer will deassert TPA upon the
first word of the cell transfer. However, when the H5/UDF provides the
address, the channel’s TPA status will not return deasserted until nine
TCLK periods after the last word of the cell transfer is complete. This
implies that once a cell transfer to a channel has begun that channel
should not be polled again until at least nine bus cycles after the transfer
is complete.
2. Once the cell transfer is started, the TENB input must remain low until
after the H5/UDF word has been transferred. After that, it is permissible
for TENB to toggle high to momentarily halt the cell transfer.
Be aware that the Any-PHY data structures are transported transparently. There
are no constraints on the contents. Therefore, data streams other than ATM
cells can be transferred across the Any-PHY interface; only the bus timing and
protocols need be respected.
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