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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
121
Data[x], with the four least significant bits of each channel on ESIG[x]
representing the signaling state (ABCD or ABAB in T1 SF mode). EFP[x] is not
available in this mode.
Figure 21
- Clock Slave: Clear Channel
TJAT
FIFO
ESIF
Egress
System
Interface
TRANSMITTER
Transmit Data[1:28]
ED[1:28]
ECLK[1:28]
TJAT
Digital PLL
Transmit CLK[1:28]
Input Timed
to ECLK[x]
In Clock Slave: Clear Channel mode, the egress interface is clocked by the
externally provided egress clock, ECLK[x]. ECLK[x] must be a 1.544 MHz clock
for T1 links or a 2.048 MHz clock for E1 links. In this mode the T1/E1 framers are
bypassed except for the TJAT which may or may not be bypassed depending on
the setting of the TJATBYP bit in the T1/E1 Egress Line Interface Options
register. Typically the TJAT would be bypassed unless jitter attenuation is
required on ECLK[x].
Figure 22
- Clock Slave: H-MVIP
TJAT
FIFO
T1-XBAS/E1-TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
Signaling Insertion,
Trunk Conditioning
Line Coding
ESIF
Egress
System
Interface
TRANSMITTER
Transmit Data[1:28]
MVED[1:7]
CASED[1:7]
CMVFP
CMVFPC
TJAT
Digital PLL
Transmit CLK[1:28]
Inputs Timed
to CMV8MCLK
CCSED
CMV8MCLK
When Clock Slave: H-MVIP mode is enabled a 8.192Mb/s H-MVIP egress
interface multiplexes up to 672 channels from 28 T1s or 21 E1s, up to 672
channel associated signaling (CAS) channels from 28 T1s or 21 E1s and
common channel signaling from up to 28 T1s or 21 E1s. The H-MVIP interfaces
use common clocks, CMV8MCLK and CMVFPC, and frame pulse, CMVFPB, for
synchronization.