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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
49
Pin Name
Type
Pin
No.
Function
CASID[1]
CASID[2]
CASID[3]
CASID[4]
CASID[5]
CASID[6]
CASID[7]
Output Y6
P20
W2
P22
V4
L19
H4
Channel Associated Signaling Ingress Data
(CASID[1:7]).
CASID[x] carries the channel associated
signaling stream extracted from all the T1 or E1
channels. Each CASID[x] signal carries CAS for four
complete T1s or E1s. CASID[x] carries the
corresponding CAS values of the channel carried in
MVID[x].
CASID[x] is aligned to the common H-MVIP
16.384Mb/s clock, CMV8MCLK, frame pulse clock,
CMVFPC, and frame pulse, CMVFPB. CASID[x] is
updated on every second rising or falling edge of
CMV8MCLK as fixed by the common MVIP frame pulse
clock, CMVFPC. The updating edge of CMV8MCLK is
selected via the CMVIDE bit in the Master Common
Ingress Serial and H-MVIP Interface Configuration
register.
CASID[1:7] shares the same pins as
ID[2,6,10,14,18,22,26].
CCSID
Output T4
Common Channel Signaling Ingress Data (CCSID).
In T1 mode CCSID carries the 28 common channel
signaling channels extracted from each of the 28 T1s.
In E1 mode CCSID carries up to 3 timeslots (15,16, 31)
from each of the 21 E1s. CCSID is formatted according
to the MVIP standard.
CCSID is aligned to the common MVIP 16.384Mb/s
clock, CMV8MCLK, frame pulse clock, CMVFPC, and
frame pulse, CMVFPB. CCSID is updated on every
second rising or falling edge of CMV8MCLK as fixed by
the common MVIP frame pulse clock, CMVFPC. The
updating edge of CMV8MCLK is selected via the
CMVIDE bit in the Master Common Ingress Serial and
H-MVIP Interface Configuration register.