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STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
218
Table 24
- DS3 Link Rate Information
Link Rate Octet
Bit #
7
6
5:4
3:0
DS3 Format
0
0
ClkRate[1:0]
Unused
Table 25
- DS3 Clock Rate Encoding
ClkRate[1:0]
DS3 Clocks / 2KHz
“00” – Nominal
22368
“01” – Fast
22372
“1x” – Slow
22364
SBI Alarms
The TEMUX transfers alarm conditions across the SBI bus for T1 and E1
tributaries. The TEMUX does not support alarm conditions across the SBI bus for
DS3 nor transparent VTs.
Table 22 show the alarm indication bit, ALM, as bit 7 of the Link Rate Octet.
Devices connecting to the TEMUX which do not support alarm indications must
set this bit to 0 on the SBI ADD bus.
The presence of an alarm condition is indicated by the ALM bit set high in the
Link Rate Octet. The absence of an alarm condition is indicated by the ALM bit
set low in the Link Rate Octet. In the egress direction the TEMUX can be
configured to use the alarm bit to force AIS on a per link basis.
T1 Tributary Mapping
Table 26 shows the format for mapping 84 T1s within the SPE octets. The DS0s
and framing bits within each T1 are easily located within this mapping for
channelized T1 applications. It is acceptable for the framing bit to not carry a
valid framing bit on the Add Bus since the physical layer device will provide this
information. Unframed T1s use the exact same format for mapping 84 T1s into
the SBI except that the T1 tributaries need not align with the frame bit and DS0
locations. The V1,V2 and V4 octets are not used to carry T1 data and are either
reserved or used for control across the interface. When enabled, the V4 octet is
the Link Rate octet of Tables 1 and 3. It carries alarm and clock phase
information across the SBI bus. The V1 and V2 octets are unused and should be