![](http://datasheet.mmic.net.cn/330000/PM8315_datasheet_16444435/PM8315_66.png)
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
51
Pin Name
Type
Pin
No.
Function
CCSED
Input
P1
Common Channel Signaling Egress Data (CCSED).
In T1 mode
CCSED carries the 28 common channel
signaling channels to be transmitted in each of the 28
T1s. In E1 mode CCSED carries up to 3 timeslots
(15,16, 31) to be transmitted in each of the 21 E1s.
CCSED is formatted according to the MVIP standard.
CCSED is aligned to the common MVIP 16.384Mb/s
clock, CMV8MCLK, frame pulse clock, CMVFPC, and
frame pulse, CMVFPB. CCSED is sampled on every
second rising or falling edge of CMV8MCLK as fixed by
the common MVIP frame pulse clock, CMVFPC. The
sampling edge of CMV8MCLK is selected via the
CMVEDE bit in the Master Common Ingress Serial and
H-MVIP Interface Configuration register.
Recovered T1 and E1 Clocks
RECVCLK1
Output D22
Recovered Clock 1 (RECVCLK1).
This clock output is
a recovered and de-jittered clock from any one of the
28 T1 framers or 21 E1 framers.
RECVCLK2
Output C22
Recovered Clock 2 (RECVCLK2).
This clock output is
a recovered and de-jittered clock from any one of the
28 T1 framers or 21 E1 framers.
Telecom Line Side Interface
LREFCLK
Input
W12
Line Reference Clock (LREFCLK).
This signal
provides reference timing for the SONET telecom bus
interface. On the incoming byte interface of the
telecom bus, LDC1J1V1, LDDATA[7:0], LDDP, LDPL,
LDTPL, LDV5, LDAIS and LAC1 are sampled of the
rising edge or LREFCLK. In the outgoing byte
interface, LADATA[7:0], LADP, LAPL, LAC1J1V1 and
LAOE are updated on the rising edge of LREFCLK.
This clock is nominally a 19.44MHz +/-20ppm clock
with a 50% duty cycle. This clock can be external
connected to SREFCLK. When in Transparent VT
mode this clock must be connected to SREFCLK.