![](http://datasheet.mmic.net.cn/330000/PM8315_datasheet_16444435/PM8315_75.png)
STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
PROPRIETARY AND CONFIDENTIAL
60
SADATA[0]
SADATA[1]
SADATA[2]
SADATA[3]
SADATA[4]
SADATA[5]
SADATA[6]
SADATA[7]
Input
D6
C7
D4
B6
A5
B5
A4
C5
System Add Bus Data (SADATA[7:0]).
The System
add data bus is a time division multiplexed bus which
carries the T1 and DS3 tributary data is byte serial
format over the SBI bus structure. This device only
monitors the add data bus during the timeslots
assigned to this device.
SADATA[7:0] is sampled on the rising edge of
SREFCLK.
This bus shares pins with ED[15,16,19,20,23,24,27,28].
SADP
Input
A2
System Add Bus Data Parity (SADP).
The system add
bus signal carries the even or odd parity for the add
bus signals SADATA[7:0], SAPL and SAV5. The
TEMUX monitors parity across all links on the add bus.
SADP is sampled on the rising edge of SREFCLK.
This signal shares a pin with signal ED[8].
SAPL
Input
B4
System Add Bus Payload Active (SAPL).
The add
bus payload active signal indicates valid data within the
SBI bus structure. This signal must be high during all
octets making up a tributary. This signal goes high
during the V3 or H3 octet of a tributary to indicate
negative timing adjustments between the tributary rate
and the fixed SBI bus structure. This signal goes low
during the octet after the V3 or H3 octet of a tributary to
indicate positive timing adjustments between the
tributary rate and the fixed SBI bus structure.
The TEMUX only monitors the add bus payload active
signal during the tributary timeslots assigned to this
device.
SAPL is sampled on the rising edge of SREFCLK.
This signal shares a pin with signal ED[12].