MC68336/376
QUEUED SERIAL MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
9-32
allows idle time between frames and eliminates idle time between transmissions. How-
ever, there is a loss of efficiency because of an additional bit-time per frame.
9.4.3.9 Internal Loop
The LOOPS bit in SCCR1 controls a feedback path in the data serial shifter. When
LOOPS is set, the SCI transmitter output is fed back into the receive serial shifter. TXD
is asserted (idle line). Both transmitter and receiver must be enabled before entering
loop mode.
9.5 QSM Initialization
After reset, the QSM remains in an idle state until initialized. A general guide for
initialization follows.
A. Global
1. Configuration QSMCR
a.Write an interrupt arbitration priority value into the IARB field.
b. Clear the FREEZE and/or STOP bits for normal operation.
2. Configure QIVR and QILR
a. Write QSPI/SCI interrupt vector number into QIVR.
b. Write QSPI (ILSPI) and SCI (ILSCI) interrupt priorities into QILR.
3. Configure PORTQS and DDRQS
a. Write a data word to PORTQS.
b. Set the direction of QSM pins used for I/O by writing to DDRQS.
4. Assign pin functions by writing to the pin assignment register PQSPAR
B. Queued Serial Peripheral Interface
1. Write appropriate values to QSPI command RAM and transmit RAM.
2. Set up the SPCR0
a. Set the bit in with the BR field.
b. Determine clock phase (CPHA), and clock polarity (CPOL).
c. Determine number of bits to be transferred in a serial operation
(BITS[3:0]).
d. Select master or slave operating mode (MSTR).
e. Enable or disable wired-OR operation (WOMQ).
3. Set up SPCR1
a. Establish a delay following serial transfer by writing to the DTL field.
b. Establish a delay before serial transfer by writing to the DSCKL field.
4. Set up SPCR2
a. Write an initial queue pointer value into the NEWQP field.
b. Write a final queue pointer value into the ENDQP field.
c. Enable or disable queue wrap-around (WREN).
d. Set wrap-around address if enabled (WRTO).
e. Enable or disable QSPI interrupt (SPIFIE).
5. Set up SPCR3
a. Enable or disable halt at end of queue (HALT).
b. Enable or disable halt and mode fault interrupts (HMIE).
c. Enable or disable loopback (LOOPQ).
6. To enable the QSPI, set the SPE bit in SPCR1.