MC68336/376
STANDBY RAM WITH TPU EMULATION
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
12-2
an address that overlaps the address of the module control register block. Writing a
valid base address to TRAMBAR[15:4] clears RAMDS and enables the array.
TRAMBAR can be written only once after a reset. This prevents runaway software
from accidentally re-mapping the array. Because the locking mechanism is activated
by the first write after a reset, the base address field should be written in a single word
operation. Writing only one-half of the register prevents the other half from being
written.
12.4 TPURAM Privilege Level
The RASP field in TRAMMCR specifies whether access to the TPURAM can be made
from supervisor mode only, or from either user or supervisor mode. If supervisor-only
access is specified, an access from user mode is ignored by the TPURAM control logic
Codes for more information concerning privilege levels.
12.5 Normal Operation
During normal operation, the TPURAM control registers and array can be accessed by
the CPU32, by byte, word, or long word. A byte or aligned word access takes one bus
cycle (two system clock cycles). A long word access requires two bus cycles.
Misaligned accesses are not permitted by the CPU32 and will result in an address
times. The TPU cannot access the array and has no effect on the operation of the
TPURAM during normal operation.
12.6 Standby Operation
Standby mode maintains the RAM array when the MCU main power supply is turned
off.
Relative voltage levels of the VDD and VSTBY pins determine whether the TPURAM is
in standby mode. TPURAM circuitry switches to the standby power source when spec-
ified limits are exceeded. The TPURAM is essentially powered by the power supply
pin with the greatest voltage (for example, VDD or VSTBY). If specified standby supply
voltage levels are maintained during the transition, there is no loss of memory when
switching occurs. The RAM array cannot be accessed while the TPURAM is powered
from VSTBY. If standby operation is not desired, connect the VSTBY pin to the VSS pin.
ISB (SRAM standby current) may exceed specified maximum standby current during
the time VDD makes the transition from normal operating level to the level specified for
standby operation. This occurs within the voltage range VSB – 0.5 V VDD VSS + 0.5
V. Typically, ISB peaks when VDD ≈ VSB – 1.5 V, and averages 1.0 mA over the tran-
sition period.
power consumption specifications.