MC68336/376
CONFIGURABLE TIMER MODULE 4
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
10-16
NOTE
Values of $0002 in the period register (PWMA2) and $0001 in the
pulse width register (PWMB2) result in the maximum possible output
frequency for a given PWM counter clock frequency.
10.9.5 PWMSM Pulse-Width Registers and Comparator
The pulse width section of the PWMSM consists of two 16-bit pulse width registers
(PWMB1 and PWMB2) and one 16-bit comparator. PWMB2 holds the current PWM
pulse width value, and PWMB1 holds the next PWM pulse width value. The next pulse
width of the output PWM signal is established by writing a value into PWMB1. PWMB2
acts as a double buffer for PWMB1, allowing the contents of PWMB1 to be changed
at any time without affecting the pulse width of the current output signal. PWMB2 is not
user accessible. PWMB1 can be read or written at any time. The new value in PWMB1
is transferred to PWMB2 on the next full cycle of the output or when a one is written to
the LOAD bit in PWMSIC.
The comparator continuously compares the contents of PWMB2 with the counter.
When a match occurs, the output flip-flop is cleared. This pulse width match completes
the pulse width, however, it does not affect the counter.
The PWM output pulse may be as short as one PWM counter clock period (PWMB2 =
$0001). It may be as long as one PWM clock period less than the PWM period. For
example, a pulse width equal to 65535 PWM clock periods can be obtained by setting
PWMB2 to $FFFF and PWMA2 to $0000.
10.9.6 PWMSM Coherency
Access to PWMSM registers can be accomplished with 16-bit transfers in most cases.
The PWMSM treats a 32-bit access as two 16-bit accesses, except when the access
is a write to the period and pulse width registers. A single long word write can set both
PWMA1 and PWMB1 because they occupy subsequent memory addresses. If the
write can be completed within the current PWM period, there is no visible effect on the
output signal. New values loaded into PWMA1 and PWMB1 will be transferred into
PWMA2 and PWMB2 at the start of the next period. If the write coincides with the end
of the current PWM period, the transfer of values from PWMA1 and PWMB1 into
PWMA2 and PWMB2 will be suppressed until the end of the next period. This prevents
undesired glitches on the output signal. During the period that is output before the sup-
pressed transfer completes, the current values in PWMA2 and PWMB2 are used.
10.9.7 PWMSM Interrupts
The FLAG bit in PWMSIC is set when a new PWM period begins and indicates that
the period and pulse width registers (PWMA1 and PWMB1) may be updated with new
values for the next output period. The PWMSM can optionally request an interrupt
when FLAG is set. To enable interrupts, set the IL[2:0] field in PWMSIC to a non-zero
value. The CTM4 compares the CPU32 IP mask value to the priority of the requested
interrupt designated by IL[2:0] to determine whether it should contend for arbitration
priority.