MC68336/376
ELECTRICAL CHARACTERISTICS
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
A-7
29A
DS, CS Negated to Data In High Impedance
88, 9
tSHDI
—48
ns
30
CLKOUT Low to Data In Invalid (Fast Cycle Ho
ld)88tCLDI
10
—
ns
30A
CLKOUT Low to Data In High Impedance
88tCLDH
—72
ns
31
DSACK[1:0] Asserted to Data In Valid10
tDADI
—46
ns
33
Clock Low to BG Asserted/Negated
tCLBAN
—23
ns
35
BR Asserted to BG Asserted (RMC Not Asserted)11
tBRAGA
1—
tcyc
37
BGACK Asserted to BG Negated
tGAGN
12
tcyc
39
BG Width Negated
tGH
2—
tcyc
39A
BG Width Asserted
tGA
1—
tcyc
46
R/W Width Asserted (Write or Read)
tRWA
115
—
ns
46A
R/W Width Asserted (Fast Write or Read Cycle)
tRWAS
70
—
ns
47A
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
tAIST
5—
ns
47B
Asynchronous Input Hold Time
tAIHT
12
—
ns
48
DSACK[1:0] Asserted to BERR, HALT Asserted12
tDABA
—30
ns
53
Data Out Hold from Clock High
tDOCH
0—
ns
54
Clock High to Data Out High Impedance
tCHDH
—23
ns
55
R/W Asserted to Data Bus Impedance Change
tRADC
32
—
ns
56
RESET Pulse Width (Reset Instruction)
tHRPW
512
—
tcyc
57
BERR Negated to HALT Negated (Rerun)
tBNHN
0—
ns
70
Clock Low to Data Bus Driven (Show)
tSCLDD
023
ns
71
Data Setup Time to Clock Low (Show)
tSCLDS
10
—
ns
72
Data Hold from Clock Low (Show)
tSCLDH
10
—
ns
73
BKPT Input Setup Time
tBKST
10
—
ns
74
BKPT Input Hold Time
tBKHT
10
—
ns
75
Mode Select Setup Time
tMSS
20
—
tcyc
76
Mode Select Hold Time
tMSH
0—
ns
77
RESET Assertion Time13
tRSTA
4—
tcyc
78
RESET Rise Time14, 15
tRSTR
—10
tcyc
NOTES:
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
2. The base configuration of the MC68336/376 requires a 20.97 MHz crystal reference.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum
allowable tXcyc period is reduced when the duty cycle of the external clock signal varies. The relationship between
external clock input duty cycle and minimum tXcyc is expressed:
Minimum tXcyc period = minimum tXCHL / (50% –external clock input duty cycle tolerance).
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during
reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high
during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference
signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
5. Address access time = (2.5 + WS) tcyc – tCHAV – tDICL
Chip select access time = (2 + WS) tcyc – tLSA – tDICL
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
Table A-6 AC Timing (Continued)
(VDD and VDDSYN = 5.0 Vdc ±5%, VSS = 0 Vdc, TA = TL to TH)
1
Num
Characteristic
Symbol
Min
Max
Unit