MC68336/376
REGISTER SUMMARY
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
D-74
CCL — Channel Conditions Latch
CCL controls the latching of channel conditions (MRL and TDL) when the CHAN reg-
ister is written.
0 = Only the pin state condition of the new channel is latched as a result of the write
CHAN register microinstruction.
1 = Pin state, MRL, and TDL conditions of the new channel are latched as a result
of a write CHAN register microinstruction.
BP, BC, BH, BL, BM, and BT — Breakpoint Enable Bits
These bits are TPU breakpoint enables. Setting a bit enables a breakpoint condition.
Table D-55 shows the different breakpoint enable bits.
D.8.4 Development Support Status Register
BKPT — Breakpoint Asserted Flag
If an internal breakpoint caused the TPU to enter the halted state, the TPU asserts the
BKPT signal on the IMB and sets the BKPT flag. BKPT remains set until the TPU
recognizes a breakpoint acknowledge cycle, or until the IMB FREEZE signal is
asserted.
PCBK —
PC Breakpoint Flag
PCBK is asserted if a breakpoint occurs because of a
PC (microprogram counter)
register match with the
PC breakpoint register. PCBK is negated when the BKPT flag
is cleared.
CHBK — Channel Register Breakpoint Flag
CHBK is asserted if a breakpoint occurs because of a CHAN register match with the
CHAN register breakpoint register. CHBK is negated when the BKPT flag is cleared.
SRBK — Service Request Breakpoint Flag
SRBK is asserted if a breakpoint occurs because of any of the service request latches
being asserted along with their corresponding enable flag in the development support
control register. SRBK is negated when the BKPT flag is cleared.
Table D-55 Breakpoint Enable Bits
Enable Bit
Function
BP
Break if
PC equals PC breakpoint register
BC
Break if CHAN register equals channel breakpoint register at beginning of state or
when CHAN is changed through microcode
BH
Break if host service latch is asserted at beginning of state
BL
Break if link service latch is asserted at beginning of state
BM
Break if MRL is asserted at beginning of state
BT
Break if TDL is asserted at beginning of state
DSSR — Development Support Status Register
$YFFE06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BKPT
PCBK CHBK SRBK
TPUF
0
RESET:
0