參數(shù)資料
型號： SPMC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 104/172頁
文件大?。?/td> 1200K
代理商： SPMC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
37
1.
The dominant interrupt source supplies a vector number and DSACK1 signals appro-
priate to the access. The CPU16 acquires the vector number.
2.
Chip-select logic asserts AVEC internally and the CPU16 generates an autovector
number corresponding to interrupt priority.
3.
The bus monitor asserts BERR and the CPU16 generates the spurious interrupt vector
number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control
to the exception handler routine.
3.9 Chip Selects
Typical microcontrollers require additional hardware to provide external chip-select signals. The
MC68HC916X1 includes five general-purpose programmable chip select circuits that can provide
2- to 13-clock cycle access to external memory and peripherals. Two additional chip select signals,
CSE and CSM, provide emulation support. Address block sizes of 2 Kbytes to 1 Mbyte can be se-
lected. However, because the CPU16 drives ADDR[23:20] to the same logic state as ADDR19,
512-Kbyte blocks are the largest usable size. Refer to 3.2.5 Emulation Support for more informa-
tion.
Chip select assertion can be synchronized with bus control signals to provide output enable, read/
write strobes, or interrupt acknowledge signals. Logic can also generate DSACK and AVEC signals
internally. A single DSACK generator is shared by all circuits. Multiple chip selects assigned to the
same address and control must have the same number of wait states. Chip selects can also be syn-
chronized with the ECLK signal available on ADDR23.
When a memory access occurs, chip select logic compares address space type, address, type of
access, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters
stored in chip select registers. If all parameters match, a chip select signal is asserted. Select sig-
nals are active low. Figure 10 shows a single chip-select circuit.
Figure 10 Chip-Select Circuit Block Diagram
CHIP SEL BLOCK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
BASE ADDRESS REGISTER
TIMING
AND
CONTROL
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
AVEC
DSACK
PIN
BUS CONTROL
INTERNAL
SIGNALS
ADDRESS
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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