參數(shù)資料
型號： SPMC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 43/172頁
文件大?。?/td> 1200K
代理商： SPMC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
137
When the LAT bit is set, ERAS also determines whether a read returns the value of the addressed lo-
cation (ERAS = 1) or the location being programmed (ERAS = 0).
The value of ERAS cannot be changed if the program/erase voltage is turned on (ENPE = 1).
LAT — Latch Control
0 = Programming latches disabled
1 = Programming latches enabled
When LAT is cleared, the BEFLASH address and data buses are connected to the IMB address and
data buses. The BEFLASH is configured for normal reads. When LAT is set, the BEFLASH address and
data buses are connected to parallel internal latches. The BEFLASH array is configured for program-
ming or erasing.
Once LAT is set, the next write to a valid BEFLASH address causes the programming circuitry to latch
both address and data. Unless control register shadow bits are to be programmed, the write must be to
an array address.
The value of LAT cannot be changed when program/erase voltage is turned on (ENPE = 1).
ENPE — Enable Program/Erase
0 = Disable program/erase voltage
1 = Apply program/erase voltage
ENPE can be set only after LAT has been set, and a write to the data and address latches has occurred.
ENPE remains cleared if these conditions are not met. While ENPE is set, the LAT, VFPE, and ERAS
bits cannot be changed, and attempts to read a BEFLASH array location in BEFLASH are ignored.
The BEFLASH bootstrap words (BFEBS[3:0]) can be used as system bootstrap vectors. When
BOOT = 0 in BFEMCR during reset, the BEFLASH responds to program space accesses of IMB
addresses $000000 to $000006 after reset. When BOOT = 1, the BEFLASH responds only to nor-
mal array and register accesses. BFEBS[3:0] can be read at any time, but the values in the words
can only be changed by programming the appropriate locations.
10.5 BEFLASH Operation
The following paragraphs describe the operation of the BEFLASH during reset, system boot, nor-
mal operation, and while it is being programmed or erased.
10.5.1 Reset Operation
Reset initializes all BEFLASH control registers. Some bits have fixed default values, and some take
values that are programmed into the associated BEFLASH shadow registers.
If the state of the STOP shadow bit is zero, and data bus pin DATA15 is pulled high during reset,
the STOP bit in BFEMCR is cleared during reset, and the module responds to accesses in the range
specified by BFEBAH and BFEBAL. When the BOOT bit is cleared, the module also responds to
bootstrap vector accesses.
BFEBS[3:0] — BEFLASH Bootstrap Words
$YFF7B0 – $YFF7B6
15
0
BOOTSTRAP VECTOR
RESET:
PROGRAMMED VALUE
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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