參數(shù)資料
型號： SPMC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 158/172頁
文件大?。?/td> 1200K
代理商： SPMC916X1CTH16
MOTOROLA
MC68HC916X1
86
MC68HC916X1TS/D
ADSTAT contains information related to the status of a conversion sequence.
SCF — Sequence Complete Flag
0 = Sequence not complete
1 = Sequence complete
SCF is set at the end of the conversion sequence when SCAN is cleared, and at the end of the first
conversion sequence when SCAN is set. SCF is cleared when ADCTL1 is written and a new conversion
sequence begins.
CCTR[2:0] — Conversion Counter Field
This field reflects the contents of the conversion counter pointer in either four or eight count conversion
sequence. The value corresponds to the number of the next result register to be written, and thus indi-
cates which channel is being converted.
CCF[7:0] — Conversion Complete Field
Each bit in this field corresponds to an A/D result register (CCF7 to RSLT7, etc.). A bit is set when con-
version for the corresponding channel is complete, and remains set until the result register is read.
RSLT[0:7] — A/D Result Registers
$YFF710–$YFF73E
The result registers are used to store data after conversion is complete. Each register can be read
from three different addresses in the register block. Data format depends on the address from which
it is read.
RJURR[0:7] — Unsigned Right-Justified Format
$YFF710–$YFF71F
Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolution. For 8-bit
conversions, bits [7:0] contain data and bits [9:8] are zero. Bits [15:10] always return zero when
read.
LJSRR[0:7] — Signed Left-Justified Format
$YFF720–$YFF72F
Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution. For 8-bit con-
versions, bits [15:8] contain data and bits [7:6] are zero. Although the ADC is unipolar, it is assumed
that the zero point is halfway between low and high reference when this format is used — for pos-
itive input, bit 15 = 0, for negative input, bit 15 = 1. Bits [5:0] always return zero when read.
LJURR[0:7] — Unsigned Left-Justified Format
$YFF730–$YFF73F
Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolution. For 8-bit
conversions, bits [15:8] contain data and bits [7:6] are zero. Bits [5:0] always return zero when read.
ADSTAT — ADC Status Register
$YFF70E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCF
NOT USED
CCTR[2:0]
CCF[7:0]
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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