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參數資料
| 型號： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁數： | 86/172頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MOTOROLA
MC68HC916X1
20
MC68HC916X1TS/D
3.2.5 Emulation Support
The SCIM contains logic that can be used to replace on-chip ports externally. The SCIM also con-
tains special support logic that allows external emulation of internal ROM. This emulation support
feature enables the development of a single-chip application in expanded mode.
Emulator mode is a special type of 16-bit expanded operation. It is entered by holding DATA10 low,
BERR high, and DATA1 low during reset. In emulator mode, all port A, B, E, G, and H data and data
direction registers and the port E pin assignment register are mapped externally. Port C data, port
F data and data direction registers, and port F pin assignment register are accessible normally in
emulator mode.
An emulator chip select (CSE) is asserted whenever any of the externally-mapped registers are ad-
dressed. The signal is asserted on the falling edge of AS. The SCIM does not respond to these ac-
cesses, allowing external logic, such as a port replacement unit (PRU) to respond. Accesses to
externally mapped registers require three clock cycles.
External ROM emulation is enabled by holding DATA1, DATA10, and DATA13 low during reset
(BERR must be held high during reset to enable the ROM module). While ROM emulation mode is
enabled, memory chip select signal CSM is asserted whenever a valid access to an address as-
signed to the masked ROM array is made.
The ROM module does not acknowledge IMB accesses while in emulation mode. This causes the
SCIM to run an external bus cycle for each access.
NOTE
The MC68HC916X1 flash modules do not yet support the emulator mode. If ROM
emulation is enabled, the CSM chip-select will be driven high at all times.
3.3 System Clock
The system clock provides timing signals for the IMB modules and for an external peripheral bus.
Because the MCU is a fully static design, register and memory contents are not affected when the
clock rate changes. System hardware and software support changes in clock rate during operation.
The system clock signal can be generated from one of two sources. An internal phase-locked loop
(PLL) can synthesize the clock from a fast reference, or the clock signal can be input directly from
an external frequency source. The fast reference is typically a 4.194 MHz crystal, but may be gen-
erated by sources other than a crystal. Keep these sources in mind while reading the rest of this
section.
Figure 5 is a block diagram of the clock submodule.
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For More Information On This Product,
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