參數(shù)資料
型號: SPMC916X1CTH16
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝: QFP-120
文件頁數(shù): 84/172頁
文件大?。?/td> 1200K
代理商: SPMC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
19
3.2.4 Single-Chip Mode
In single-chip mode, when BERR = 0 during reset, ADDR[18:3] are configured as 8-bit I/O ports
(port A and port B) and DATA[15:0] are configured as 8-bit I/O ports (port G and port H). There is
no external data bus path. Expanded mode configuration options are not available: I/O ports A, B,
E, F, G, and H are always selected. BERR can be tied low permanently to select single-chip mode.
Table 13 is a summary of SCIM pin functions during single-chip operation.
1. These pins have only one reset configuration in 8-bit expanded mode.
Table 12 8-Bit Expanded Mode Reset Configuration
Pin(s) Affected
Select Pin
Default Function
(Pin Held High)
Alternate Function
(Pin Held Low)
BR/CS0
FC0/CS3/PC0
FC1/PC1
FC2/CS5/PC2
N/A1
CS0
CS3
FC1
CS5
CS0
CS3
FC1
CS5
ADDR19/CS6/PC0
ADDR23/CS10/ECLK
N/A1
CS6
CS10
CS6
CS10
DSACK1/PE1
DS/PE4
AS/PE5
SIZ0/PE6
SIZ1/PE7
DATA8
DSACK1
DS
AS
SIZ0
SIZ1
PE1
PE4
PE5
PE6
PE7
MODCLK/PF0
IRQ[7:6]/PF[7:6]
DATA9
MODCLK
IRQ[7:6]
PF0
PF[7:6]
BGACK/CSE
BG/CSM
N/A1
BGACK
BG
BGACK
BG
Table 13 Single-Chip Mode Reset Configuration
Pin(s) Affected
Function
ADDR[18:11]
PA[7:0]
ADDR[10:3]
PB[7:0]
BR/CS0
CS0
FC0/CS3/PC0
FC1/PC1
FC2/CS5/PC2
ADDR19/CS6/PC3
PC[3:0]
ADDR23/CS10/ECLK
DSACK1/PE1
DS/PE4
AS/PE5
SIZ0/PE6
SIZ1/PE7
PE[7:4], PE1
MODCLK/PF0
IRQ[7:6]/PF[7:6]
PF0
PF[7:6]
DATA[15:8]
PG[7:0]
DATA[7:0]
PH[7:0]
BGACK, CSE
BG/CSM
BGACK
BG
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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