參數(shù)資料
型號： SPMC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 110/172頁
文件大?。?/td> 1200K
代理商： SPMC916X1CTH16
MOTOROLA
MC68HC916X1
42
MC68HC916X1TS/D
The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode selected
1 = Synchronous mode selected
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
In synchronous mode, the DSACK field is not used because a bus cycle is only performed as a syn-
chronous operation. When a match condition occurs on a chip select programmed for synchronous op-
eration, the chip select signals the EBI that an E-clock cycle is pending.
BYTE[1:0] — Upper/Lower Byte Option
This field is used only when the chip select 16-bit port option is selected in the pin assignment register.
Table 26 lists upper/lower byte options.
R/W[1:0] — Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
Table 27 shows the options.
STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address
strobe causes chip select to be asserted synchronized with address strobe. Selecting data strobe caus-
es chip select to be asserted synchronized with data strobe.
DSACK[3:0] — Data and Size Acknowledge
This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus
timing with internal DSACK generation by controlling the number of wait states that are inserted to op-
timize bus speed in a particular application. Table 28 shows the DSACK[3:0] field encoding. A no-wait
encoding (%0000) corresponds to a three clock-cycle bus. The fast termination encoding (%1110) cor-
responds to a two clock-cycle bus. Microcontroller modules typically respond at this rate, but fast termi-
nation can also be used to access fast external memory.
Table 26 Byte Field Bit Encoding
BYTE[1:0]
Description
00
Disable
01
Lower Byte
10
Upper Byte
11
Both Bytes
Table 27 Read/Write Bit Encodings
R/W[1:0]
Description
00
Disable
01
Read Only
10
Write Only
11
Read/Write
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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