參數(shù)資料
型號： SPMC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 53/172頁
文件大?。?/td> 1200K
代理商： SPMC916X1CTH16
MOTOROLA
MC68HC916X1
146
MC68HC916X1TS/D
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
2. The base configuration of the MC68HC916X1 requires a 4.194 MHz crystal reference.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum al-
lowable tXcyc period is reduced when the duty cycle of the external clock varies. The relationship between external
clock input duty cycle and minimum tXcyc is expressed:
Minimum tXcyc period = minimum tXCHL / (50% – external clock input duty cycle tolerance).
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during
reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high
during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference
signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
31
DSACK1 Asserted to Data In Valid9
tDADI
—50
ns
33
Clock Low to BG Asserted/Negated
tCLBAN
—29
ns
35
BR Asserted to BG Asserted10
tBRAGA
1
—tcyc
37
BGACK Asserted to BG Negated
tGAGN
1
2tcyc
39
BG Width Negated
tGH
2
—tcyc
39A
BG Width Asserted
tGA
1
—tcyc
46
R/W Width Asserted (Write or Read)
tRWA
150
—
ns
46A
R/W Width Asserted (Fast Write or Read Cycle)
tRWAS
90
—
ns
47A
Asynchronous Input Setup Time
BR, BGACK, DSACK1, BERR
tAIST
5—
ns
47B
Asynchronous Input Hold Time
tAIHT
15
—
ns
48
DSACK1 Asserted to BERR Asserted11
tDABA
—30
ns
53
Data Out Hold from Clock High
tDOCH
0—
ns
54
Clock High to Data Out High Impedance
tCHDH
—28
ns
55
R/W Asserted to Data Bus Impedance Change
tRADC
40
—
ns
70
Clock Low to Data Bus Driven (Show Cycle)
tSCLDD
029
ns
71
Data Setup Time to Clock Low (Show Cycle)
tSCLDS
15
—
ns
72
Data Hold from Clock Low (Show Cycle)
tSCLDH
10
—
ns
73
BKPT Input Setup Time
tBKST
15
—
ns
74
BKPT Input Hold Time
tBKHT
10
—
ns
75
Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)tMSS
20
—tcyc
76
Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)tMSH
0—
ns
77
RESET Assertion Time12
tRSTA
4
—tcyc
78
RESET Rise Time13
tRSTR
—
10
tcyc
100
CLKOUT High to Phase 1 Asserted14
tCHP1A
340
ns
101
CLKOUT High to Phase 2 Asserted14
tCHP2A
3
40
ns
102
Phase 1 Valid to AS or DS Asserted14
tP1VSA
10
—ns
103
Phase 2 Valid to AS or DS Asserted14
tP2VSN
10
—ns
104
AS or DS Valid to Phase 1 Negated14
tSAP1N
10
—ns
105
AS or DS Negated to Phase 2 Negated14
tSNP2N
10
—ns
Table 78 AC Timing (Continued)
(V
DD
and V
DDSYN
= 5.0 Vdc
±10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H)
1
Num
Characteristic
Symbol
Min
Max
Unit
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
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