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參數(shù)資料
| 型號(hào)： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁(yè)數(shù)： | 99/172頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MOTOROLA
MC68HC916X1
32
MC68HC916X1TS/D
It is not possible to perform transfers of word operands to an 8-bit port on the MC68HC916X1 be-
cause the DSACK0 pin is not present and therefore cannot be asserted to acknowledge the trans-
fer. This limitation can be overcome by using SCIM chip-select logic to generate DSACK for such
transfers.
3.7 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. The MCU per-
forms resets with a combination of hardware and software. The SCIM determines whether a reset
is valid, asserts control signals, performs basic system configuration and boot ROM selection based
on hardware mode-select inputs, then passes control to the CPU16.
Reset occurs when an active low logic level on the RESET pin is clocked into the SCIM. Resets are
gated by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchro-
nous reset can occur on any clock edge. Synchronous resets are timed to occur at the end of bus
cycles. If there is no clock when RESET is asserted, reset does not occur until the clock starts. Re-
sets are clocked to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset
exception, and cannot be restarted. Only essential tasks are performed during reset exception pro-
cessing. Other initialization tasks must be accomplished by the exception handler routine.
3.7.1 SCIM Reset Mode Selection
The logic states of certain MCU pins during reset determine SCIM operating configuration. Refer to
3.2.1 Operating Modes for more information.
3.7.2 MCU Module Pin Function During Reset
Module pins usually default to port functions, and input/output ports are set to input state. This is
accomplished by disabling pin functions in the appropriate control registers, and by clearing the ap-
propriate port data direction registers. For more information, refer to the sections of this technical
summary that present information about the individual modules. Table 20 is a summary of module
pin functions out of reset.
1. Operands in parentheses are ignored by the CPU16 during read cycles.
2. Three-byte transfer cases occur only as a result of long word to byte transfer.
3. The CPU16 treats misaligned long-word transfers as two misaligned word transfers.
Table 19 Operand Alignment
Transfer Case
SIZ1
SIZ0
ADDR0
DATA[15:8]
DATA[7:0]
Byte to 16-Bit Port (Even)
0
1
0
OP0
(OP0)1
Byte to 16-Bit Port (Odd)
0
1
OP0
Word to 16-Bit Port (Aligned)
1
0
OP0
OP1
Word to 16-Bit Port (Misaligned)
1
0
1
OP0
3 Byte to 16-Bit Port (Aligned)2
1
0
OP0
OP1
3 Byte to 16-Bit Port (Misaligned)2
111
OP0
Long Word to 16-Bit Port (Aligned)
0
OP0
OP1
Long Word to 16-Bit Port (Misaligned)3
101
OP0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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