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參數(shù)資料
| 型號： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁數(shù)： | 30/172頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
125
The control register blocks for the 16 Kbyte and 32 Kbyte flash EEPROM modules start at locations
$YFF800 and $YFF820, respectively. The following register descriptions apply to the correspond-
ing register in either control block. References to FEExMCR, for example, apply to both FEE1MCR
(in the 16 Kbyte module) and FEE2MCR (in the 32 Kbyte module.)
A number of control register bits have associated bits in “shadow” registers. The values of the shad-
ow bits determine the reset states of the control register bits. Shadow registers are programmed or
erased in the same manner as a location in the array, using the address of the corresponding con-
trol registers. When a shadow register is programmed, the data is not written to the corresponding
control register. The new data is not copied into the control register until the next reset. The contents
of shadow registers are erased when the array is erased.
Configuration information is specified and programmed independently of the array. After reset, reg-
isters in the control block that contain writable bits can be modified. Writes to these registers do not
affect the associated shadow register. Certain registers can be written only when LOCK = 0 or
STOP = 1 in FEExMCR.
9.4 Flash EEPROM Array
The base address registers specify the starting address of the flash EEPROM array. The user pro-
grams the reset base address. The base address of the 16 Kbyte array must be on a 16 Kbyte
boundary; the base address of the 32 Kbyte array must be on a 32 Kbyte boundary. Behavior will
be indeterminate if one flash EEPROM array overlaps the other.
The base address must also be set so that an array does not overlap a flash EEPROM control block
in the data space memory map. If an array does overlap a control block, accesses to the 32 bytes
in the array that is overlapped are ignored, allowing the flash EEPROM control blocks to remain
accessible. If the array overlaps the control block of another module, the results will be indetermi-
nate.
9.5 Flash EEPROM Registers
In the following register diagrams, bits with reset states determined by shadow bits are shaded, and
the reset state is annotated “SB”.
The flash EEPROM module configuration registers (FEE1MCR, FEE2MCR) control module config-
uration. This register can be written only when LOCK = 0. All active bits in the FEExMCR take val-
ues from the associated shadow register during reset.
STOP — Stop Mode Control
0 = Normal operation
1 = Low-power stop operation
STOP can be set either by pulling data bus pin DATA14 low during reset (for both flash EEPROM mod-
ules) or by the corresponding shadow bit. The array can be re-enabled by clearing STOP. If STOP is
set during programming or erasing, the program/erase voltage is automatically turned off. However, the
ENPE control bit in FEExCTL remains set. When STOP is cleared, the program/erase voltage is auto-
matically turned back on if ENPE is set.
FEE1MCR, FEE2MCR — Flash EEPROM Module Configuration Registers
$YFF800, $YFF820
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP FRZ
0
BOOT LOCK
0
ASPC[1:0]
WAIT[1:0]
0
RESET:
DATA14
+ SB
0
SB
0
SB
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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