參數(shù)資料
型號: SPMC916X1CTH16
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝: QFP-120
文件頁數(shù): 93/172頁
文件大?。?/td> 1200K
代理商: SPMC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
27
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period. Table 15 gives
the ratio for each combination of SWP and SWT bits.
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor Enable
0 = Disable bus monitor function for internal to external bus cycles.
1 = Enable bus monitor function for internal to external bus cycles.
BMT[1:0] — Bus Monitor Timing
This field selects a bus monitor time-out period as shown in Table 16.
3.4.1 Bus Monitor
The internal bus monitor checks for excessively long response times during normal bus cycles
(DSACK1) and during IACK cycles. The monitor asserts the internal BERR signal if response time
is excessive.
DSACK1 response times are measured in clock cycles. The maximum allowable response time can
be selected by setting BMT[1:0].
The monitor does not check DSACK1 response on the external bus unless the CPU16 initiates the
bus cycle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cy-
cles. If a system contains external bus masters, an external bus monitor must be implemented, and
the internal to external bus monitor option must be disabled.
Table 15 Software Watchdog Timeout Period Divide Ratio
SWP
SWT[1:0]
Ratio
000
29
001
211
010
213
011
215
100
218
101
220
110
222
111
224
Table 16 Bus Monitor Timeout Period
BMT[1:0]
Time-Out
0 0
64 System Clocks
0 1
32 System Clocks
1 0
16 System Clocks
1 1
8 System Clocks
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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