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參數(shù)資料
| 型號(hào)： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁(yè)數(shù)： | 6/172頁(yè) |
| 文件大小： | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
103
QILR determines the priority level of interrupts requested by the QSM.
ILQSPI[2:0] — Interrupt Level for QSPI
ILQSPI determines the priority of QSPI interrupts. This field must be given a value between $0 (inter-
rupts disabled) to $7 (highest priority).
ILSCI[2:0] — Interrupt Level of SCI
ILSCI determines the priority of SCI interrupts. This field must be given a value between $0 (interrupts
disabled) to $7 (highest priority).
If ILQSPI and ILSCI are the same nonzero value, and both submodules simultaneously request inter-
rupt service, QSPI has priority.
At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the ex-
ception table. This vector is selected until QIVR is written. A user-defined vector ($40–$FF) should
be written to QIVR during QSM initialization.
After initialization, QIVR determines which two vectors in the exception vector table are to be used
for QSM interrupts. The QSPI and SCI submodules have separate interrupt vectors adjacent to
each other. Both submodules use the same interrupt vector with the least significant bit (LSB) de-
termined by the submodule causing the interrupt.
The value of INTV0 used during an interrupt-acknowledge cycle is supplied by the QSM. During an
interrupt-acknowledge cycle, INTV[7:1] are driven on DATA[7:1] IMB lines. DATA0 is negated for
an SCI interrupt and asserted for a QSPI interrupt. Writes to INTV0 have no meaning or effect.
Reads of INTV0 return a value of one.
7.3.2 Pin Control Registers
The QSM uses nine pins, eight of which form a parallel port (PORTQS) on the MCU. Although these
pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose I/
O on a pin-by-pin basis.
Pins used for general-purpose I/O must not be assigned to the QSPI by register PQSPAR. To avoid
driving incorrect data, the first byte to be output must be written before DDRQS is configured.
DDRQS must then be written to determine the direction of data flow and to output the value con-
tained in register PORTQS. Subsequent data for output is written to PORTQS.
QILR — QSM Interrupt Levels Register
$YFFC04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ILQSPI[2:0]
ILSCI[2:0]
QIVR
RESET:
0
QIVR — QSM Interrupt Vector Register
$YFFC05
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
QILR
INTV[7:0]
RESET:
0
1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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