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參數(shù)資料
| 型號： | SPMC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁數(shù)： | 40/172頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | SPMC916X1CTH16 |
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MOTOROLA
MC68HC916X1
134
MC68HC916X1TS/D
10.2 BEFLASH Control Block
The BEFLASH module control block contains five registers: the BEFLASH module configuration
register (BFEMCR), the BEFLASH test register (BFETST), the BEFLASH array base address reg-
isters (BFEBAH and BFEBAL), and the BEFLASH control register (BFECTL). Four additional words
in the control block can contain bootstrap information when the BEFLASH is used as bootstrap
memory.
Each register in the control block has an associated shadow register that is physically located in a
spare BEFLASH row. During reset, fields within the registers are loaded with default information
from the shadow registers. Shadow registers are programmed or erased in the same manner as
locations in the BEFLASH array, using the address of the corresponding control registers. When a
shadow register is programmed, the data is not written to the corresponding control register. The
new data is not copied into the control register until the next reset. The contents of shadow registers
are erased whenever the BEFLASH array is erased.
Configuration information is specified and programmed independently of the BEFLASH array. After
reset, registers in the control block that contain writable bits can be modified. Writes to these reg-
isters do not affect the associated shadow register. Certain registers are writable only when the
LOCK bit in BFEMCR is disabled or when the STOP bit in BFEMCR is set. These restrictions are
noted in the individual register descriptions.
10.3 BEFLASH Array
The base address registers specify the starting address of the BEFLASH array. A default base ad-
dress can be programmed into the base address shadow registers. The array base address must
be on a 2 Kbyte boundary. Because the states of ADDR[23:20] follow the state of ADDR19, ad-
dresses in the range $080000 to $F7FFFF cannot be accessed by the CPU16. If the BEFLASH ar-
ray is mapped to these addresses, the system must be reset before the array can be accessed.
Avoid using a base address value that causes the array to overlap control registers. If a portion of
the array overlaps the EEPROM register block, the registers remain accessible, but accesses to
that portion of the array are ignored. If the array overlaps the control block of another module, how-
ever, those registers may become inaccessible. If the BEFLASH array overlaps another memory
array (RAM or flash EEPROM), proper access to one or both arrays may not be possible.
10.4 BEFLASH Registers
In the following register diagrams, the reset value SB indicates that a bit assumes the value of its
associated shadow bit during reset.
This register can be written only when the control block is not write-locked (when LOCK = 0). All
active bits take values from the associated shadow register during reset.
STOP — Stop Mode Control
0 = Normal operation
1 = Low-power stop operation
STOP can be set either by pulling data bus pin DATA15 low during reset or by the corresponding shad-
ow bit. The EEPROM array is inaccessible during low-power stop. The array can be re-enabled by
BFEMCR — BEFLASH Module Configuration Register
$YFF7A0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP
FRZ
0
BOOT LOCK
0
ASPC[1:0]
0
RESET:
DATA15+
SB
0
SB
0
SB
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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