參數(shù)資料
型號(hào): STM32W108HBU7
廠(chǎng)商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, QCC40
封裝: 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-40
文件頁(yè)數(shù): 174/198頁(yè)
文件大?。?/td> 2871K
代理商: STM32W108HBU7
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STM32W108CB, STM32W108HB
Serial interfaces
Doc ID 16252 Rev 3
To initiate (re)start and stop segments, set the SC_TWISTART or SC_TWISTOP bit in the
SCx_TWICTRL1 register, then wait until the bit is clear. Alternatively, the SC_TWICMDFIN
bit in the SCx_TWISTAT can be used for waiting.
To initiate a transmit segment, write the data to the SCx_DATA data register, then set the
SC_TWISEND bit in the SCx_TWICTRL1 register, and finally wait until the bit is clear.
Alternatively the SC_TWITXFIN bit in the SCx_TWISTAT register can be used for waiting.
To initiate a receive segment, set the SC_TWIRECV bit in the SCx_TWICTRL1 register, wait
until it is clear, and then read from the SCx_DATA register. Alternatively, the SC_TWIRXFIN
bit in the SCx_TWISTAT register can be used for waiting. Now the SC_TWIRXNAK bit in the
SCx_TWISTAT register indicates if a NACK or ACK was received from a TWI slave device.
9.5.3
Interrupts
TWI master controller interrupts are generated on the following events:
Bus command (SC_TWISTART/SC_TWISTOP) completed (0 to 1 transition of
SC_TWICMDFIN)
Character transmitted and slave device responded with NACK
Character transmitted (0 to 1 transition of SC_TWITXFIN)
Character received (0 to 1 transition of SC_TWIRXFIN)
Received and lost character while receive FIFO was full (receive overrun error)
Transmitted character while transmit FIFO was empty (transmit underrun error)
To enable CPU interrupts, set the desired interrupt bits in the second level INT_SCxCFG
register, and enable the top level SCx interrupt in the NVIC by writing the INT_SCx bit in the
INT_CFGSET register.
9.6
Universal asynchronous receiver / transmitter (UART)
The SC1 UART is enabled by writing 1 to SC1_MODE. The SC2 serial controller does not
include UART functions.
The UART supports the following features:
Flexible baud rate clock (300 bps to 921.6 bps)
Data bits (7 or 8)
Parity bits (none, odd, or even)
Stop bits (1 or 2)
False start bit and noise filtering
Receive and transmit FIFOs
Optional RTS/CTS flow control
Receive and transmit DMA channels
The UART uses two signals to transmit and receive serial data:
TXD (Transmitted Data) - serial data received by the STM32W108
RXD (Received Data) - serial data sent by the STM32W108
If RTS/CTS flow control is enabled, these two signals are also used:
nRTS (Request To Send) - indicates the STM32W108 is able to receive data RXD
nCTS (Clear To Send) - inhibits sending data from the STM32W108 if not asserted
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